Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

368 The Quintessential PIC Microcontroller

The Option register, also in Bank 1, is set up to assign the prescaler to the Watchdog and extend its time-out period by ×128. The Timer 0 counter is set to be clocked from T0CKI on a negative-going edge. Finally, back in Bank 0 Timer 0 itself is set to E8h (i.e. −24 decimal) so that 24 can pulses will cause it to overflow and cause an interrupt. Both INTCON flags T0IE and GIE are then set to enable the interrupt.

The main background program commences with a clrwdt instruction. Provided that the background endless loop is no longer than 7 × 128 = 0.8961 s, the minimum Watchdog period, then time-out will not occur.

With the initialization code in situ all that remains is to implement the Interrupt Service Routine (ISR) that will be automaticlly entered after each batch of 24 cans. When this occurs, Timer 0 will set T0IF and the PIC will jump to the Interrupt vector at 004h. In our initialization code we have placed a goto ISR at this point and so named the routine in Program 13.1.

Program 13.1 The bean counter Interrupt Service Routine.

; *************************************************************

;*************************************************************

;First save context in usual way

;************************************************************

;The core code

; ************************************************************

13. Time is of the Essence 371

•Reset Timer 0 interrupt flag.

•Return from interrupt.

2.ELSE a hardware interrupt form peak picker.

•Copy ji y count into general-purpose file registers.

•Zero Timer 0.

•Set New flag.

•Reset hardware interrupt flag.

•Return from interrupt.

Both bytes in COUNT:COUNT+1 are copied into the two data file registers DATUM:DATUM+1 when a hardware interrupt is received and the Ji y count/Timer 0 is then zeroed ready for the next event. When the background program polls file register NEW and finds a non-zero datum then it knows that a fresh count is ready for collection. It then, for instance, could send it to a serial EEPROM as in Example 12.3 on page 351 or down a serial link to a PC for subsequent processing and display.

Most midand high-range PICs have at least two additional timer/counters and associated circuitry with the following properties.

Timer 1

This 16-bit counter has its own dedicated oscillator and programmable prescaler. Its state can be sampled by an external event and it can control the state of a pin when it reaches a pedefined value.

Timer 2

This 8-bit counter has both programmable pre and postscaler facilities. Its count length can be set by the programmer and it may be used to generate a pulse-width modulated output with no on-going software overhead.

Capture/Compare/PWM

Both timers can be used in conjunction with additional logic called Capture/Compare/Pulse Width Modulation (CCP) to implement the Timer 1 sample instant (Capture), the Timer 1 roll-over value (Compare) and the automatic PWM generation from Timer 2.

Timer 1 comprises a primary 16-bit counter implemented as a pair of file registers at File 0Eh for the low byte TMR1L and File 0Fh for the high byte TMR1H. The Timer 1 CONtrol register TMR1CON at File 10h configures Timer 1 as shown in Fig. 13.5.

Timer 1 has the option (T1OSCEN in T1CON[3] = 1) of using a separate oscillator from the main PIC oscillator. This avoids having to pick the main crystal to suit the timer, as we did in our Timer 0 bean counter example. Some older PIC devices, such as the PIC16C74A, require the RC0/T1CKI pin to be set as input for the oscillator to function. Newer devices, such as the PIC16C74B, do not need this configuration. The Timer 1 oscillator has a maximum frequency of 200 kHz but is typically used with

372 The Quintessential PIC Microcontroller

1 ÷1, ÷2, ÷4, ÷8

T1OS1

EN

Fig. 13.5 Functional equivalent circuit for Timer 1

a 32.768 kHz watch crystal. Where this is the case, Timer 1 will overflow in 2 seconds with a prescale ratio of 1:1 (T1CKPS[1:0] = 00) and a maximum of 16 s for a prescale ratio of 1:8 (T1CKPS[1:0] = 11). When overflow takes place, the Timer 1 Interrupt Flag in the Peripheral Interrupt Register 1 PIR1[0] is set. If the corresponding TMR1IE mask in the Peripheral Interrupt Enable 1 register PIE1[0] then an interrupt will occur. All interrupt flags and mask bits for Timer 1, Timer 2 and their related CCP modules are located in PIR1, PIR2, PIE1 and PIE2 as shown in Fig 14.10(b) on page 408. To enable all these interrupts the PEIE (PEripheral Interrupt Enable) bit in INTCON[6] must be set as well as the overall GIE global mask bit in INTCON[7]. The latter should be 0 if the only action required is to awaken the PIC from its Sleep state, but PEIE must still be set.

The Timer 1 oscillator adds approximately 20 µa current drain which is a consideration that is especially important if it is intended to use Timer 1 to awaken the processor. Where power consumption is at a premium then a low-power external oscillator should be considered. In this situation with T1OSCEN = 0 the external oscillator should drive the T1CKI pin. Limitations on the upper frequency of such an input are similar to that discussed for Timer 0. Alternatively the internal PIC clock can be used if TMR1CS is zeroed (the reset condition), but of course this stops when the processor is in its Sleep state.

Output from the programmable prescaler is by default synchronized to the internal clock giving a 2-cycle delay. However, unlike Timer 0 this synchronization shift register can be bypassed with T1SYNC set to 1.