Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

364 The Quintessential PIC Microcontroller

Resetting initializes the Watchdog timer and zeros the postscaler so it’s not necessary to issue an extra clrwdt as we have done above. However, the initializing process will add to the time it takes to get into the normal main code and the normal loop clrwdt, thus an extra clrwdt at the end of any initializing code is useful insurance.

In the 12-bit PIC family the Watchdog time-out was the only way short of a Manual reset to awaken a device in the Sleep state. The sleep instruction resets the Watchdog and postscaler counters to give a full timeout period when entering the Sleep state. As the Watchdog oscillator is stand-alone it continues to run while the PIC is asleep. After the ordained period a Watchdog reset occurs and the PIC resumes execution with the instruction following sleep. If necessary the programmer can determine that the time-out occurred during the Sleep state by examining the TO bit.

The Watchdog awaken mechanism is not so important for the midand high-range PIC families. These can be awakened by an external interrupt, and where applicable the Timer 1 and Analog modules, both of which have the option of a self-standing clock oscillator. Where the watchdog is enabled and used in the Sleep mode the designer should be aware that the typical current consumption4 rises from typically 1.5 µA (24 µA maximum) to 10.5 µA (42 µA maximum). Where long-term battery operation is required (for example, see SAQ 12.6 on page 360) this presents serious problems. Running the processor continually at the lower frequency of 32.768 kHz with the Watchdog disabled takes typically 52 µA (105 µA maximum) in comparison.

The original 12-bit PIC16C5XX family features a basic 8-bit counter/- prescaler which was called a Real-Time Clock/Counter. Although this term was still used in the early 14-bit PIC16CXXX data sheets, the introduction of additional timers lead to the more consistent term Timer 0 (TMR0). However, the term RTCC is still to be found as a relic in older textbooks and software. For example, the CCS C compiler sets the Timer 0 clock source to external low-going edge with a prescale value of 4 by calling setup_counters(rtcc_ext_l_to_h, rtcc_div_4);.

From Fig. 13.3 we see that Timer 0 comprises a primary 8-bit counter located at File 1 in tandem with an optional 8-bit prescaler counter. This gives eight selectable clock rates into the primary counter as selected by the three PS[2:0] bits in OPTION_REG. This Timer 0 prescaler is actually

4The PIC16C74 with VDD = 4 V, −40◦C to +85◦C.

Fig. 13.3 Simplified equivalent circuit for Timer 0.

the same circuit as the Watchdog’s postscaler5 and PSA in OPTION_REG[3] must be set to 0 to assign the prescaler to Timer 0.

The prescaler is assigned to the Watchdog timer by default on Poweron/Manual reset and in this situation the primary counter is either clocked by the internal cycle clock Fosc at a rate XTAL/4 or from an outside source via the Timer 0 Clock Input RA4/T0CKI pin. The Timer 0 Clock Select

T0SC bit at OPTION_REG[5] is used to select the internal/external mode. When clocked from outside, the active edge is set using the Timer 0 Set Edge T0SE bit at OPTION_REG[4].

In order to synchronize the outside clock to the internal Timer 0 primary counter, a 2-stage shift register is used at the latter’s clock input.

This causes a 2 × Fosc/4 delay; 1 µs with an 8 MHz crystal. Where the primary counter is directly connected to the internal clock, this will cause

a 2-count delay before anything happens after a datum is written into Timer 0 at File 1. This synchronization is such that Timer 0 may be read from or written to in the normal way without interfering with any possible count action.

When the primary counter overflows (11111111 → 00000000) the Timer 0 Interrupt Flag T0IF is set. This event can be sensed by polling

INTCON[2] or if the Timer 0 Interrupt Enable mask bit T0IE in INTCON[5] is set an interrupt will automatically be generated – see Fig. 7.4 on page 178.

An external clock signal going directly into the primary counter should

be high for at least 2Tosc +20 ns and low for at least the same time. Thus for a 8 MHz crystal, Thigh should be 270 ns and the same for Tlow; a max-

5The PIC18CXXX family use separate scalers for the Watchdog timer and Timer 0.

366 The Quintessential PIC Microcontroller

imum frequency of 1.8 MHz. When the prescaler is used this minimum

total period of 4Tosc + 40 ns can be divided by the prescaler ratio. The input waveform is subject only to a minimum 10 ns pulse width. Thus

with a ÷256 setting, a nominally 50 MHz signal at T0CKI will be counted. When assigned to Timer 0 the prescaler is not readable, so the timer is not strictly a 16-bit counter. Reading Timer 0 does not a ect the prescaler but any instruction writing to it (eg. clrf 1, movwf 1) will both clear the

prescaler and the clock synchronizer.

As the prescaler is assigned to the Watchdog on Power on/Manual reset it can be subsequently changed over by clearing PSA. However, it is possible that this change-over could cause a Watchdog reset even if it is disabled. Microchip therefore recommend that the change-over be preceded by a clrwdt instruction; for example:

The code shows the prescaler divides clock input by four from the T0CKI pin, and incrementing on the \ . It is also possible to change the prescaler over from Timer 0 to the Watchdog timer ‘on the fly’. In the same manner the clrwdt should be executed before altering OPTION_REG to avoid a spurious Watchdog reset.

Timer 0 is mainly used either to count external events or to determine the period between external events. it can also be used to time software toggling port pins for precisely known durations, without tying up the processor in time-wasting delay routines.

Fig. 13.4 Counting cans of beans on a conveyer belt.