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12. One Bit at a Time 357

The various DS1820 functions, such as Convert (44h), Read temperature (BEh), are initiated by the Master sending the appropriate data as 8-bit codes, each byte comprising a Start condition ( \ ) and eight Write

slots, as shown in Fig. 12.24(b). As in the I2C case, the data line DQ is pulled high with a pull-up resistor and the Master simulates the logic 1 state by changing its port line from low to input (see Fig. 12.14(b)). In this state the Master can listen to data sent by the Slave as shown in Fig. 12.24(c).

For our example we are required to write two subroutines that will respectively write a byte to a 1-Wire Slave and read a byte from the Slave.

Solution

From Fig. 12.24(b) we see that writing a bit to a Slave involves the following tasks:

1.The Master starts the process by forcing the data line low for at least 1 µs.

2.The Master either keeps the line low (Write 0) or releases the line (Write 1) for 60 – 120 µs.

3.The Slave reads the line state between 15 – 45 µs later.

4.The Master releases the line (if Write 0) for at least 1 µs to relax the system.

The subroutines of Program 12.16 assume that the port line driving DQ has been set up as described on page 325 for the I2C bus to give the two states as hard low and open circuit – pulled up high. Also we assume that we have the delay macro Delay_us in situ which gives a Kµs delay, where K is the parameter passed to the macro.

Delay_us macro

K

; K is the

number of usec delay

local

DELAY_US_LOOP

movlw

(K*XTAL)/(4*3)+1 ;

1˜

DELAY_US_LOOP

addlw

-1

; Decrement count: N˜

btfss

STATUS,Z ; to zero

: N + 1˜

goto

DELAY_US_LOOP ;

: 2(N-1)˜

endm

Both subroutines begin by driving DQ low for a minimum of 1 µS, defining the Start condition. Writing a single bit to DQ occurs in a slot which has a duration of 60 – 120 µs, and commences with DQ either low or released to be pulled high, defining a Write-0 or Write-1 condition. The Slave samples the state of the data line sometime after 15 µs into the slot. Although the duration of the slot is not critical, care needs to be taken as a low duration of between 480 and 960 µs is interpreted by the Slave as a Reset command (see SAQ 12.3).

358 The Quintessential PIC Microcontroller

Program 12.16 Reading and writing on a 1-Wire system.

; *************************************************************

; *

FUNCTION:

Writes a

byte datum to a 1-Wire slave

*

; *

RESOURCE:

macro

Delay_us giving N microsecond delay

*

;

*

ENTRY

:

Datum

is

in

DATA_OUT

*

;

*

EXIT

:

DATA_OUT

is

zero, W, STATUS altered

*

; *************************************************************

WRITE_1W movlw

8

; Loop count

movwf

COUNT

W_LOOP bcf

INDF,DAT

; Low edge signals Start

Delay_us

1

; for 1us

rrf

DATA_OUT,f

; LSB first shift into Carry

btfsc

STATUS,C

; Was it a 1?

bsf

INDF,DAT

; IF it was THEN output high

Delay_us

d’60’

; Hold for 60us

bsf

INDF,DAT

; Release line to go high

Delay_us

1

; Relax for 1us

decfsz

COUNT,f

; Repeat eight times

goto

W_LOOP

return

; *************************************************************

; *

FUNCTION:

Reads a byte datum from a 1-Wire slave

*

; *

RESOURCE:

macro Delay_us giving N microsecond delay

*

;

*

ENTRY

:

None

*

;

*

EXIT

:

Datum is in DATA_IN, W, STATUS altered

*

; *************************************************************

READ_1W

movlw

8

; Loop count

movwf

COUNT

R_LOOP

bcf

INDF,DAT

; Low edge signals Start

Delay_us

1

; for 1us

bsf

INDF,DAT

; Release line

Delay_us

8

; Wait 8us for Slave to O/P data

bcf

STATUS,C

; Clear Carry

btfsc

INDF,DAT

; Check input state

bsf

STATUS,C

; IF high THEN set Carry

rrf

DATA_IN,f

; Shift bit in -> LSB

Delay_us

d’48’

; Wait to end of slot

decfsz

COUNT,f

; Repeat eight times

goto

R_LOOP

return

Eight Write slots are used with a 1 µs relax period interval to transmit the byte, each slot’s state following the bit rotated into the Carry flag of the datum byte DATA_OUT. After eight shift/output cycles the process terminates.

Reading from a Slave involves the following tasks:

1.The Master starts the process by forcing the data line low for at least 1 µs.

2.The Master then listens to data placed on the line by the Slave which is valid for up to 15 µs after the Start edge.

3.The Slave releases the line after 15 µs which should be pulled high by the end of the 60 µs slot.

12. One Bit at a Time 359

4. The Master waits for a minimum of 1 µs before commencing the next slot.

The input subroutine READ_1W follows this task list, sampling the data line sometime before 15 µs into the slot, at which time the Slave’s data should have settled to the appropriate voltage level. Each bit is used to set the Carry flag which is then shifted into DATA_IN. After eight sample/shift loops, DATA_IN has the received byte datum.

Unlike the I2C bus, the 1-Wire architecture is designed for a single Master. However, 1-Wire Slaves have device addresses comprising a 64bit unique code as part of an internal ROM. The first eight bits are a 1-Wire family code – the DS1820 code is 10h. The following 48 bits are a unique serial number and the last eight bits are an error checking byte.

Self-assessment questions

12.1Rewrite Program 11.3 on page 288 but based on the SPI hardware of Fig. 12.5. Hint: Rather than shifting in whole bytes it may be more e cient to simply shift in and test on a bit-by-bit basis.

12.2Show how you could connect four MAX518 ADCs (see Fig 12.16) on the one I2C circuit and how channel 1 on the third ADC could be written to.

12.3Communications along a 1-Wire link begins with a Reset operation where the Master pulls the line low for 480 – 960 µs after which the line is released. The Slave then responds by dragging the line low

after no more than 60 µs delay. This low persists for a further 60

– 240 µs after which the Slave releases this line. Design a subroutine that will do this procedure when called. Assume the resources of Program 12.16 are available to you.

12.4 Parity is a technique whereby the number of digits in a word is always either even or odd. This is accomplished by adding an extra bit which is calculated by the transmission software to be 0 or 1 to meet this overall criterion. For instance, for odd parity of an 8-bit word 01101111 we have 1 01101111. The receiver will check that all nine received bits have an odd count. If one bit (or any odd number) has been corrupted by noise, then a parity error is said to have occurred.

Based on the PIC USART, write software to set the asynchronous protocol to 9 bit word and calculate the odd one’s parity bit of DATA_OUT which should be placed in TX9D of the TXSTA register prior to the loading of the data into TXREG and transmission.

360The Quintessential PIC Microcontroller

12.5Rewrite the subroutine GETCHAR of Program 12.11 as an interrupt service routine called GETCH. Compare the two approaches.

12.6A certain data logger is to sample temperature once per 15 minutes. The power supply current consumption is reduced by us-

ing a PIC16LC74 (Low-voltage) part at a VDD of 3 V and a crystal of 32.780 MHz. Under these conditions the current consumption with the Timer 1 running is a maximum of 70 µA (45 µA typical). A I2C EEPROM is to be used to store the data as it is read but is only powered on at sample time – by using a spare port line as the EEPROM’s power supply. The logger is to be left submerged at the bottom of a lake for six months before being recovered. Can you choose an appropriate 24LCXXX EEPROM and estimate the capacity of the 3 V battery in mA-hours?

12.7When the data logger alluded to in the last SAQ is brought back to base it is to be connected to a PC in the manner illustrated in Fig. 12.21 and the data uploaded via the serial port. The data terminal running on the PC has set the serial port to 4800 baud with a 8-bit word. The data logger is to transmit an ASCII character for STX (02h) to the PC which if ready is to respond by sending back the code for ACK (00h). After this handshake the logger sends the EEPROM data beginning at address 000h with two ASCII characters representing each stored byte. For example if the byte is A9h then the codes 41h followed by 39h are transmitted; i.e. ’A’ ’9’. When the logger encounters the EEPROM datum FFh it is to terminate the conversation with the PC by sending the ASCII code for EOT (04h). Using the code of Programs 12.15 and 12.12 as a guide write a suitable program.

12.8A typical Liquid Crystal Display, for example the Hitachi LM032L, is

shown in Fig. 12.25. Show how you could use a PIC16F84 to give the LCD display an I2C interface.

D3D2D1D0 R/W E RS

Vcc

Vo

Vss

Fig. 12.25 A LCD display.

CHAPTER 13

Time is of the Essence

Of crucial importance in many systems are time-related functions. This may manifest itself in the measurement of duration, event counting or control of an external physical event for known periods. An example of the former would be the time between pulses generated by the teeth on a flywheel to measure engine speed for a tachometer.

Where time is of the essence these functions are often best implemented by using hardware counters to time events. In this chapter we will look at the various timer modules which are available to the mid-range PIC family. After completion you should:

•Know how a Watchdog timer improves the robustness of a MCU-based system and how to use the integral PIC device.

•Be able to use the basic 8-bit Timer 0 module as both a counter and timer.

•Understand the function of the 16-bit Timer 1 module and its interaction with the Capture/Compare/PWM (CCP) modules.

•Be able to use the 8-bit Timer 2 module together with the CCP modules to generate a pulse-width modulated output.

Many MCU-based systems are hosted in an electrically hostile environment with noise induced outside both through logic lines and the power supply. Our example of an auto tachometer is typical of this situation, with induction from the high-voltage ignition sparks and alternator sourced ripple in the battery supply. No matter what precautions in shielding and filtering are taken, it is inevitable that on occasion the MCU will jump out of its proper location in Program memory and ‘run amok’ with potentially serious consequences on the controlled system.1 In some cases this is little more serious than requiring a manual reset.2 However, this is not possible in many situations; for example, in a pacemaker implanted in the patient’s body!

One solution to this problem is to use a counter/oscillator which resets the processor when it overflows. If the software is arranged to clear this counter on a regular basis so that overflow never occurs then the

1The same can happen due to software bugs.

2As in a Window’s PC.

362 The Quintessential PIC Microcontroller

MCU never resets. If something happens and the MCU jumps out of its normal loop then the counter will overflow and the MCU will be reset to its starting point. This counter circuit is given the name Watchdog timer.3

clrwdt

STATUS

File 03h

Reset PIC

reset up-Power

S 4

TO

R

Postscaler

÷128

÷64

÷32

÷16

÷8

÷4

÷2

÷1

110

101

100

011

010

001

111

000

R

CNTR8 C+ R

G

wdt fuse

Watchdog timer oscillator/counter 18 ms (nominal)

0

PS0

1

PS1

2

PS2

1 3 OPTION_REG

File 81h

Fig. 13.1 The integral PIC Watchdog timer.

Rather than rely on external Watchdog timers, all PIC MCUs, even the early 12-bit PIC16C5XX family, have an integral module as illustrated in Fig. 13.1. A built-in oscillator separate from the processor clock runs continually if the Watchdog timer is enabled, with a nominal period of 18 ms. The integral capacitor/resistor timing network is not tightly specified and as a consequence the period will vary with device process, temperature and supply voltage from a minimum of 7 ms (lowest temperature −40◦C,

highest VDD 6 V) up to a maximum of 33 ms (highest temperature +85◦C, lowest VDD 2 V) – see Fig. 15.8 on page 448.

The Watchdog oscillator is followed by an 8-bit Watchdog postscaler counter. This prescaler be set to give Watchdog counter overflow timeout periods going up in powers of two up to nominally 18 × 128 ≈ 2.3 s

– 0.9 s minimum, 4.2 s maximum. The actual value is selected by the programmer using the PS[2:0] (Pre/Post Scaler rate Select) bits in the Option register (OPTION_REG) – see Fig. 13.2. The Watchdog postscaler and counter are both cleared with the clrwdt (CLeaR WatchDoG Timer) instruction and issuing this at regular intervals is the mechanism whereby the programmer prevents time-out.

3Other approaches typically are based on a retriggerable monostable.

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