Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

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To get to within 0.2% of the final voltage; that is 0.5 of an 8-bit quantum level error, takes approximately 7 × τ. Taken with the 5 µs settling time, the minimum sample time before starting a conversion is around 12 µs. This can be lowered a little by reducing the source resistance. This resistance should not exceed 10 kΩ as pin leakage IL = ±1 µA will give a voltage o set approaching the quantum voltage step. Once charged, the sampling switches disconnect the input pin from the network to hold the voltage constant, so that voltage changes during the conversion period do not a ect the outcome. Thus in a multi-channel ADC module, the channel selection can be changed at this time.

During the sample (S) period, the top capacitor electrodes are held to 0 V and bottom electrodes are charged to Vin. The change-over to the hold (H) position grounds the bottom electrodes and allows the top electrodes to float. The voltage across a capacitor can only change if charge is transferred across electrodes, ∆Q = C∆V. Thus the change in voltage ∆V = −Vin at the bottom electrodes is matched at the top floating electrodes, which now become 0 − Vin, as charge cannot flow in or out of the floating top electrodes. Thus at the start of the conversion process the inverting input of the analog comparator is −Vin.

The successive approximation network at the heart of the A/D converter is shown in a simplified form in Fig. 14.6. The step-by-step process is sequenced by a shift register (SRG, see Fig. 2.20 on page 36) when the programmer sets the GO/DONE bit3 in the ADCON0 register (A/D CONtrol 0).4 As the Control shift register is clocked, the single 1 moves down to activate each step in the sequence:

Hold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Ready Sample

The capacitor network is switched to Hold and each capacitor, beginning

with the largest value, is switched to Vref in turn. The outcome of the comparator then determines the state of the corresponding bit in the Succes-

sive Approximation Register (SAR). The process is detailed in Fig. 14.7. After eight set-try-reset actions, the outcome in the SAR is transferred to the Analog to Digital RESult (ADRES) register in File 0Ah. The GO/DONE flag is now cleared to indicate the End Of Conversion and the ADIF flag set. Finally, the analog input is again switched back into the capacitor network (Sample).

The total conversion time is approximately ten times the clocking rate tAD of the sequencer shift register. The minimum clocking period is 1.6 µs (≈ 600 kHz) for all but the older 2 µs PIC16C71/711 devices. There is no specified lower clocking frequency, but as charge slowly leaks away from the network capacitors, a tAD of more than nominally 20 µs (50 kHz)

3GO/DONE can also be set by the CCP2 Comparison special event, see page 375.

4The ADCON0/ADCON1/ADRES registers are at File 1Fh/File 9Fh/File 1Eh respectively in all PIC16C7XX devices except the PIC16C71/710/711, where the corresponding locations are File 08h/File 88h/File 09h.

400 The Quintessential PIC Microcontroller

Fig. 14.6 Simplified view of the A/D converter.

should be avoided. From Fig. 14.8 we see that the ADC clock can be derived from one of four sources using the ADCS1:0 (A/D Clock Select) bits in the ADCON0 SPR. The first three of these are fractions of the MCU clock rate and the fourth is a stand-alone CR oscillator with a nominal tAD of 4 µs.

One of the first tasks a programmer must do is to determine the clocking rate by setting the ADCS1:0 bits appropriately. Table 14.2 shows suggested settings for four typical PIC crystal frequencies. If A/D conversion time is critical then the PIC crystal may be chosen to give the fastest con-

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Table 14.2: ADC clocking frequency versus device crystal frequency.

version time. For example, a 5 MHz crystal with ADCS1:0 = 01 gives a tAD of 1.6 µs.

The internal ADC module CR clock is typically used where the main crystal is below 1 MHz. This separate clock source also allows a conversion to be completed when the PIC is in its Sleep mode, as the main processor oscillator is switched o in this situation. In this case the end of conversion interrupt can be used to awaken the MCU. This gives a relatively quiet environment during the conversion and for this reason is often used even where the processor crystal is above 1 MHz – see Program 14.4.

For lowest current consumption, especially during the Sleep mode, the ADC module should be switched o when not in use by clearing the ADON bit in ADCON0. ADON is cleared on Reset, so needs to be set when the module is to be activated.

The conversion process is illustrated in Fig. 14.7. As we have seen in Fig. 14.5, at the end of the sample period the top plates of the capacitor array are at −Vin and the bottom plates are disconnected but at zero potential. As an example let us assume that Vin is 0.4285Vref.

1.The process begins by switching in Vref into the lower plate of the largest capacitor as controlled by the SAR8 latch in Fig. 14.6. This causes an injection of charge ∆Q = CtotalVref, which is identical across both the 8-unit capacitor C1 and the rest of the capacitors which also have a parallel value of 8 units in Fig. 14.7. Thus the voltage

at node N rises by Vref/2 to −0.485 + 0.5 = +0.07125Vref. In general ∆VN = Vref Ck/Ctotal. The comparator output is now logic 0 and the SAQ8 latch is consequently cleared, reversing the Vref/2 step.

2.SAQ4 switches Vref into the next highest capacitor giving a Vref/4 step at N (124 ). The resulting voltage of −0.485 + 0.25 = −0.178Vref giving a comparator output of logic 1 and SAR4 remains set with the node voltage staying at −0.1785Vref.

3.SAQ2 switches Vref into the second lowest capacitor giving a Vref/8 step at N (162 ). The resulting voltage of −0.1785+0.125 = −0.0535Vref giving a comparator output of logic 1 and SAR2 remains set with the node voltage staying at −0.0535Vref.