Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

14. Take the Rough with the Smooth 403

4.SAQ1 switches Vref into the lowest capacitor giving a Vref/16 step at N (161 ). The resulting voltage of −0.0535+0.0625 = +0.009Vref giving a comparator output of logic 0 and SAR1 is cleared and the Vref/16 step is reversed.

The state of the SAR of 0110b or 0.375Vref represents the best 4-bit fit to Vin = 0.4285Vref. The residue 0.0535Vref is the quantizing error. Most

MCUs use an 8-bit capacitor array. In principle the technique can readily be extended to higher resolutions, but in practice the di culty in matching ever greater capacitors and internal logic noise means the majority of processors use 8-bit resolution. However, a few MCU devices5 do have 10 or 12-bit converters. External successive-approximation devices with 12 or more bits resolution, usually using a resistor ladder network, are readily available, but are relatively expensive.

Matching of the array capacitors, o sets and resistance of internal switches, leakage currents and analog comparator non-linearities all contribute to errors in the conversion process. It is beyond the scope of this text to analyze the various measures of error but the device data sheet lists absolute error, defined as the sum of all component error measures, as better than ±1 LSB. This guarantees that the transfer is monotonic; that is the binary code will never move in the reverse direction for any

change ∆Vin of input voltage. This error figure is for Vref = VDD; if Vref is lower than VDD then accuracy deteriorates, although values down to 3 V

will give acceptable results in most cases. Accuracy can be improved, especially when the internal CR oscillator is used, if the conversion is done while the PIC is in its Sleep mode.

The standard PIC ADC module has eight input channels with any one selected for conversion according to the 3-bit Channel Select code CHS2:0 in the ADCON0 register, as shown in Fig. 14.8. 28-pin footprint PICs, such as the PIC16C73, can only access the bottom five channels. The PIC16C71 line of 18-pin footprint6 and 12C67X devices have an earlier 4-channel module with CHS2 missing. The PIC16C774 uses ADCON0[1] as CHS3.

The input analog channels AN4:0 are shared with the Port A digital inputs RA4:0 and AN7:5 with Port E RE2:0 in 40-pin devices. AN3 is special in that it can be used as the reference voltage input if configured accordingly by PCFG0 = 1 (Port ConFiGuration) bit in the ADCON1 register. Like all port configuration registers it is normally set up only once at the beginning of the program and it is therefore located in the less convenient Bank 1 Data memory. Any such low-noise external Vref should be in the range 3 V → VDD + 0.3 V – see Fig. 14.17. For best accuracy it should be as high as possible; a value of 5.12 V will give a 20 mV per bit resolution.

5For example the PIC16F87X devices have a 10-bit ADC and the PIC16C77X have a 12-bit ADC with internal precision positive and negative reference voltages.

6The PIC16C71/710/711/715.

14. Take the Rough with the Smooth 405

Table 14.3: Configuring the ADC port pins in the PIC16C73/74 devices.

page 273) into its linear range and the resulting large current could cause irreversible damage.

Other PIC devices with an ADC module may have di erent settings and numbers of PCFG bits. For example the 8-pin footprint PIC12C67X devices with a 4-channel ADC module can configure individual pins as analog or digital to best use scarce resources. The PIC16C71X line has only the two PCFG bits whilst the PIC16C774 has four.

Fig. 14.9 Configuring the analog inputs for Port A and Port E.

We can see from Fig. 14.9 that an I/O pin configured as an analog input from ADCON1 simply disables the digital input bu er (compare with Fig. 11.2 on page 273). No other circuitry is a ected. From this we can make the following deductions.

406 The Quintessential PIC Microcontroller

•A port pin configured as analog will read as logic 0 due to the disabled digital input bu er.

•The TRIS bu er is not a ected and thus the appropriate TRIS bits should be 1; that is the direction of the port pins configured as analog

should be set to input to prevent contention between the nalog Vin and the digital state of the Data flip flop.

•The ADC can read an analog voltage at the pin even if that pin has not been configured as analog. However, the still active digital input bu er may consume an excessive current outside of the device’s specification.

Using Fig. 14.8 as the programmer’s model we can now deduce the hardware-software interaction in order to action a conversion. Assuming first that interrupts are not being used, the following steps can be identified:

1.Configure ADC module.

•Set up port pins as analog/voltage reference (ADCON1).

•Select ADC conversion clock source (ADCON0).

•Select ADC input channel (ADCON0).

•Turn on ADC module (ADCON0).

2.Wait for the required acquisition time, typically 12 µs.

3.Start conversion by setting the GO/DONE bit.

4.Wait for ADC conversion to complete by polling the GO/DONE bit for low.

5.Read the ADRES register.

6.For next conversion go to step 1 or step 2 as required.

As an example, consider that we wish to read the channel n analog voltage (RAn) of a PIC16C74 and output the equivalent digital value at

Port B. The main crystal is 20 MHz and VDD is to be used as Vref.

The listing of Program 14.1 assumes that the ADC module has been initialized at reset with startup code of the form:

which sets up the pin configuration according to the PCFGn settings of Table 14.3 to enable all eight ADC channels. The ADCON0 is initialized to 10 000 001b to set the module clock source as the crystal frequency/32;

i.e. 2032 = 625 kHz (giving a conversion time of ≈ 12 +15µs), channel zero

and the module is turned on. With an initial zero value of GO/DONE no conversion is actioned. The initial channel value is irrelevant.

With the module initialized, the subroutine listed in Program 14.1 simply copies the contents of W, truncated to three bits for robustness, into a temporary location TEMP. There it is logic shifted left three places to align the channel number with the CHSn bits in the ADCON0 register.