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434 The Quintessential PIC Microcontroller

EECON1 register

Fig. 15.2 The PIC16F8X EECON1 register.

EEPROM CONtrol register 2 EECON2

This register located at File 89h is not physically implemented – it always reads as zero. Rather the action of writing the successive code pattern 01010101 → 10101010 with no interruption is used to unlock the Write cycle. This arcane incantation is deliberately designed to convolute the process as security against unintended alterations in the data.

In order to read a specified datum from the EEPROM module we have to implement software to execute the task list:

1.Copy the target cell’s address to EEADR.

2.Set RD to 1 to initiate the Read cycle.

3.RD is automatically cleared immediately and the target 8-bit datum can be read from EEDATA any time from the next instruction cycle as convenient.

Program 15.1 Retrieving a byte from the EEPROM Data module.

; ************************************************************

; ************************************************************

15. To Have and to Hold 435

Subroutine EE_GET in Program 15.1 directly implements this process and illustrates the return of the datum from the EEPROM cell to the Working register. The datum will remain in EEDATA until the register is reused.

Writing data to the EEPROM Data module is deliberately made more Byzantine to reduce the chance of a spurious Write corrupting the data due to a software bug or processor malfunction because of, say, a power glitch. The task list to write a datum to a specified cell is:

1.Copy the target cell address to EEADR.

2.Set WREN in EECON1[2] to enable the Write process.

3.Disable all interrupts.

4.Send 55hto EECON2.

5.Send AAhto EECON2.

6.Set WR to initiate the Write cycle.

7.Clear WREN.

8.Enable interrupts.

9.Wait until WR returns to zero, signalling the completion of the Write cycle, and exit.

The Write cycle will not initiate if the interlock sequence items 4 – 6 is not exactly followed without interference. For example; in an interruptdriven system an interruption during the interlock sequence will abort the Write cycle. Thus in this situation interrupts should be disabled by clearing GIE until the Write cycle has been initiated, otherwise this step can be omitted.

If desired the completion of the Write cycle can be used to interrupt the processor. This is enabled by setting the EEIE mask bit in INTCON[6]. When the interrupt flag EEIF, located in EECON1[4], is set in the normal way then the interrupt is generated. It should be cleared in the ISR.

It is possible that the processor is reset, for example by a Watchdog overflow, before the Write cycle is complete. In this situation, the EEPROM datum may be corrupt. The WRERR flag in EECON1[3] will be set if the Write operation has been prematurely terminated with a Reset action. If this is not the case, when the cycle is complete the datum may be read back and verified to give extra security. The WREN bit may be cleared at this point to help prevent an accidental Write. Doing this before the Write is complete will not a ect the operation.

Program 15.2 implements this task list. Both EEDATA and EEADR are set up by the caller program with the byte data and address. The subroutine is not pulled out until the Write cycle has completed; typically 4 ms. This ensures that these SPRs will not be altered during the cycle which may possibly give an erroneous outcome.

In order to illustrate these concepts we will repeat Example 12.3 on page 351 replacing the external serial EEPROM with the internal module. We will assume that the odometer count is located at EEPROM cells 10

– 12h.

436 The Quintessential PIC Microcontroller

Program 15.2 Putting a byte into the EEPROM Data module.

; ************************************************************

; ************************************************************

The coding shown in Program 15.3 makes use of the two subroutines EE_GET and EE_PUT to read and subsequently write the three odometer bytes from the EEPROM Data module. The address of the first (highest) byte is copied into EEADR at the beginning of the subroutine and is subsequently incremented and decremented in situ to point to the appropriate datum.

Once the 3-byte odometer state has been fetched and copied into memory it is incremented in exactly the same manner as in Program 12.15 on page 354. The augmented array is then written back into EEPROM in the opposite sense as it was read, with EEADR being decremented. The EE_PUT subroutine checks that the Write cycle has been completed before returning and thus timing need not be checked by the calling program.

As well as altering data under program control it is possible to initialize the state of the EEPROM Data module when the executable program is being externally blasted into the Program memory; as illustrated in Fig. 10.5(a) on page 261. The area of Program memory beyond the user Program store belongs to the special test/configuration memory space 2000h– 30FFh and can be accessed only during external programming. In Fig. 10.5(b) we observed that the Configuration fuse word is located at 2007h. The EEPROM module also lies in this space located at 2100h– 21FFh. For example, to store the value of sine every 10◦ between 0◦ and 90◦ as part of the program source code we have:

where the assembler directive de (Data EEPROM) specifies the comma delimited list of data. Once the PIC has been programmed, the contents of the EEPROM Data module will look like Fig. 15.3.

Program 15.3 Incrementing the non-volatile odometer count in Data EEPROM.

;************************************************************

;FUNCTION: Adds one onto the triple-precision odometer total*

; ************************************************************

EXTRA_MILE movlw movwf call movwf incf call movwf incf call movwf

; Now increment 3-byte array

; Put the augmented odometer count back in Data EEPROM

15. To Have and to Hold 439

PIC16F874

This 40-pin device has a 8 Kbyte flash Program store and 256-byte EEPROM Data store together with 192 file registers. It is pin compatible with the PIC16C74 device.

PIC16F876

This 28-pin device is the same as the PIC16F873 but with twice the Program store capacity at 8 Kbytes and double the EEPROM Data module capacity at 256 bytes The file register store is increased to 368 file registers.

PIC16F877

This is a 40-pin version of the PIC16F876. Key EEPROM properties are:

•100,000 minimum EEPROM Data module Erase/Write cycle endurance per cell.

•1000 minimum flash EEPROM Program store Erase/Write cycle endurance.

•Maximum Write/Erase time 8 ms (typical 4 ms) for both the Data module and flash memory.

Of particular note is the endurance limit of 1000 Write cycles for the flash EEPROM. Whilst this is entirely satisfactory when changing the device’s program, it is a limitation for some non-volatile data storage situations. Thus flash Program memory storage is more applicable to constant data, such as the sine lookup table, rather than for information that requires frequent update, such as the odometer.

Flash EEPROM has a smaller geometry than normal EEPROM. Whilst this speeds up its operation, charges which eventually trap in the floating gate insulation have a disproportional e ect on the storage mechanism and leads to earlier deterioration.

Figure 15.4 shows the PIC16F87X EEPROM Data module with the flash Program store superimposed. This form of representation is used as the EEDATA and EEADR registers are common to both EEPROM arrays. Of course, the flash Program store is larger both in the number of cells (8 Kbytes against 256 bytes) and in cell size (14 bits against 8 bits). Thus both Data and Address registers have the high-end extensions EEDATH and EEADRH respectively to cope with this additional capacity.

As we shall see, the process of reading from and writing to either array is similar. The target module is chosen using the EEPGD (EEProgram/Data) control bit control bit in EECON1[7]. Apart from this additional bit and the removal of the EEIF interrupt flag to the PIR2 register, the EECON1 register of Fig. 15.5 is identical to the basic PIC16F8X version shown in Fig. 15.2. The virtual EECON2 interlock register remains the same.