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422 The Quintessential PIC Microcontroller

Example 14.2

Using C coding show how a digitized reading from Channel 3 of a PIC16C74 can be acquired with the processor in its Sleep state.

Solution

The CCS compiler uses the sleep() function to put the MCU to sleep

– this simply translates to the sleep instruction. A Sleep conversion cannot be implemented using the read_adc() function of Program 14.5 as this continuously polls the GO/DONE flag until it drops low. Instead we need to set and clear individual interrupt related bits before going to sleep in the manner outlined in the assembly-level Program 14.4. On wakening the state of ADRES can then be read ‘manually’.

Program 14.7 Sleep conversion in C.

#define ADRES *(unsigned int *)0x1e int main()

{

unsigned int i; set_tris_a(0x0E); setup_adc(ADC_CLOCK_INTERNAL);

setup_adc_ports(RA0_RA1_RA3_ANALOG); set_adc_channel(3);

disable_interrupts(GLOBAL);/* Disable all ints (GIE & PEIE=1)*/ ADIF = 0;

enable_interrupts(INT_ADC);

GO = 1; sleep();

i = ADRES;

}

Coding for this specification is shown in Program 14.7. Here the GO/DONE, PEIE and ADIF bits are defined using the #bit directive. This time the script ADC_CLOCK_INTERNAL is used with the setup_adc() internal function to select the internal CR clock for the DAC module, as necessary for the Sleep conversion.

The internal function disable_interrupts(GLOBAL) clears both GIE and PEIE mask bits. The complementary enable_interrupts(GLOBAL)

14. Take the Rough with the Smooth 423

sets both bits but we need to enable the PEIE only and leave GIE cleared. This is implemented by the ‘bit-twiddling’ statement PEIE=1;. Similarly, clearing the ADIF flag is directly actioned by ADIF=0;. Before calling sleep() the statement GO=1;manually starts the conversion. After sleep() the ADRES register is read giving the required digitized equivalent.

Example 14.3

The analog input channel voltage range for the PIC16C7X/71X devices10

is limited to the positive range 0–Vref, where Vref can either be the internal VDD voltage or an external voltage at RA3 in the range 3–VDD. Many situa-

tions require a digitized mapping from bipolar analog signals. Design a simple resistive network to translate a bipolar voltage range of ±10 V to a unipolar range of 0–5 V, assuming Vref is +5 V.

Solution

+10V

Vref = 5V

-10V

R2

Fig. 14.15 A level-shifting resistor network.

One possibility is shown in Fig. 14.15. In calculating the value of the three resistors, the following transfer relationships must be adhered to:

1.The value of Vref must appear at the summing node attenuated by 2 when Vin is zero; that is half scale. Thus a zero voltage 0 V 10000000b. To do this R1 paralleled with R2 must have the same resistance as R3; i.e.:

R3 = R1//R2

10The 16C77X devices can be configured to accept bipolar input analog voltages.

424 The Quintessential PIC Microcontroller

2.Vin must be attenuated by the gain of the system G, where the input range is ±G×Vref. In our case G = 2. Thus using the potential divider relationship:

2G = R1 + (R2//R3)/(R2//R3)

After some manipulation we have:

Of course we have three unknowns and only two equations so we have to start o by choosing a value for one of them below 10 kΩ, which is the maximum recommended value for input resistance. Picking 5 kΩ for R3

gives R2 as 2 × 5 = 10 kΩ and R2 as R1/(G − 1) = 10 kΩ. For the situation ±5 V 5 V then R1 = ∞ and R2 = R3.

Example 14.4

As part of a smart biomedical monitor, the peak analog value of an electro-cardiogram (ECG) signal is to be determined anew for each cycle. This R-point (see Fig. 7.1 on page 172) maximum value is to be output from Port B and RA5 is to be pulsed high whenever this value is being updated. Assuming that a PIC16C73/4 is used to implement the intelligence, the the ECG signal (conditioned as shown in Fig. 14.15) connected to Channel 1 RA1, devise a possible strategy. Timer 0 is being used to interrupt the processor at nominally 100 times per second (see Program 13.2 on page 370) design a suitable ISR to implement your strategy.

Solution

As in any biomedical parameter the ECG signal will vary from cycle to cycle in gain, shape and period. Even if this were not so, imperfections in the data acquisition system, notably the skin electrodes, can cause slow baseline (dc) drift. Thus the threshold at which the signal is to be tracked to its peak R-value must be reset at some sensible fraction of its previous peak during the period following the last update.

One possibility is shown in Fig. 14.16. Here the threshold is slowly decremented after the peak to ensure that a following peak of lower amplitude is not missed. On the basis of a lowest ECG rate of 40 beats per minute (period 1.5 s) if we reduce the threshold by one bit each two samples then the maximum reduction would be a count of 75 at a sample rate of 100 per second. To do this the threshold value THRESHOLD in Program 14.8 is stored as a double-byte number of form integer:fraction and half an integer (i.e. fraction = 10000000b) subtracted in each sample where the peak value MAXIMUM is not updated.

The task list implemented by this listing is:

1. DO a conversion to get ANALOG.