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428The Quintessential PIC Microcontroller

14.2A programmer writing an ISR-based handler for an analog module has replaced the retfie instruction in Program 14.2 by return. What e ect will this have?

14.3Real world analog signals are noisy. In practice this means that some form of filtering or smoothing is frequently required. In any circumstance noise coming in from outside should not have any appreciable frequency components above half the sampling rate since such noise will be frequency shifted back into the baseband as shown in Fig. 14.4. Such low-pass filtering must be applied to the signal before the A/D conversion.

Although this external anti-alias filter must by definition be implemented using hardware circuitry (such as a CR network), noise within the passband can be smoothed out using software filtering routines. One simple approach to digital filtering is to take multiple readings and average them to give a composite outcome. For example, 16

readings summed and shifted right four times (÷16) would reduce random noise by a factor of √16 = 4.

Another approach well known to staticians, is to take a moving average; for example, of a stock price over a month interval. An e cient algorithm of this type is a 3-point average:

Array[i] = S4n + Sn2−1 + Sn4−2

where Sn is the nth sample from the analog module.

Show how you could modify the GET_ANALOG subroutine to remember the last samples from the two previous calls and return the smoothed value.

14.4 It has been suggested that as part of the ECG monitor of Example 14.4 that a MAX506 DAC be used to introduce an automatic gain control function preceding the PIC’s analog input. The aim of the AVC is to keep the peak of the analog input between 34 and 78 full scale. How might you go about implementing this subsystem? Hint: Remember that each channel of a MAX506 is the product of its digital input and Vref and that the latter can vary between 0 V and VDD.

14.5How could the time between ECG peaks be measured with a resolution of 10 ms and output at one of the parallel ports as an extension of Example 14.4?

14.6An input analog sinusoid signal, conditioned as shown in Fig. 14.15, is to be full-wave rectified; that is voltages that were originally negative are to have their sign changed. Design a routine to do this assuming that the input voltage is available at ADRES and the processed output is to be presented via Port B to a DAC.


14. Take the Rough with the Smooth 429

14.7Write a C coded program after Program 14.5 to compare two analog

voltages at Channel 0 and 1 bringing RA2 high when V0 > V2, RA3 likewise for V0 == V1 and RA4 for V0 < V1. Assume a PIC16C71 device with a clock frequency of 10 MHz. The PIC16C71 can be set to make RA0 and RA1 analog (RA0_RA1_ANALOG) with the rest digital.

14.8Figure 14.17 is based on Fig. 10 of Microchip’s application note AN546

Using the Analog-to-Digital (A/D) Converter as a means of providing an external voltage reference source for power-sensitive applications. How do you think the circuit works and what factors govern the choice of current limiting resistor?

RB1

D

R

VREF/RA3

Z

C

C = 10 to 100 nF

Fig. 14.17 A controllable external voltage circuit.

14.9 Microchip recommend that where possible channle 0 RA0/AN0 should not be used in the PIC16C71 due to possible noise problems. Can you see why this is so and can you think of any way around this problem?

RB4

10

9

RB3

RB5

11

8

RB1

RB6

12

7

RB0/INT

RB7

13

6

VDD

VDD

14

5

VSS

OSC2/CLKOUT

15

4

MCLR

OSC1/CLKIN

16

3

RA4/T0CKI

RA0/AN0

17

2

RA3/AN3/Vref

RA1/AN1

18

1

RA2/AN2

Fig. 14.18 Pinning for the PIC16C71.



CHAPTER 15

To Have and to Hold

Several midand high-range PIC devices feature a small EEPROM scratchpad memory that can be controlled and accessed indirectly via SpecialPurpose Registers (SPRs) in the same manner as other peripheral devices. An integral non-volatile scratchpad enables the programmer to read and modify static data, such as the odometer tally in a car, which needs to be retained in the absence of a power supply – see Example 12.3 on page 351. Although this facility can be implemented using an external EEPROM memory, such as the 24LC01 of Fig. 12.22 on page 352, where only a modest amount of non-volatile data needs to be stored, integral EEPROM storage increases reliability and reduces cost, size and power requirements.

Our objective here is to examine the non-volatile storage facilities available to members of the mid-range PIC family. After reading this chapter you will:

Be familiar with the characteristics of the EEPROM Data memory.

Know how to both read and write data to the EEPROM module.

Understand how the main flash EEPROM Program memory can be used in some devices to store and retrieve non-volatile data.

Be able to contrast the EEPROM Data module and flash Program memory as a location for non-volatile data.

The PIC16C83/4 introduced in 1994, was the first PIC device to use EEPROM technology for its main Program store. As we gave seen in Fig. 2.12 on page 27, Electrically Erasable PROM is similar to EPROM but does not require UV radiation to erase data. Although EEPROM technology is more expensive than EPROM, its use in implementing the Program store is convenient in prototyping and educational/hobbyist applications. Along with this innovation, an EEPROM peripheral module was featured which enabled the programmer to store up to 64 bytes of nonvolatile data independently of the normal file register memory.

The PIC16C83/4 and its analogous flash EEPROM memory successor, the PIC16F83/4, remained the only EEPROM family member until the introduction of the PIC16F87X in 1998. As of 2000, Microchip were committed to introduce flash EEPROM versions of most of their standard midand high-range devices. Thus, for example, the PIC16F74 will shadow the PIC16C74 processor.

432 The Quintessential PIC Microcontroller

In this chapter we will use the 18-pin PIC16F83/4, 28-pin PIC16F873/6 and 40-pin PIC16F874/7, here denoted the PIC16C8X and PIC16F87X lines respectively, as our exemplar. However, before examining the details, it is instructive to look at an application requiring the use of non-volatile storage. A good example of this is the smart card of Fig. 12.1 on page 305. Here we need to store, amongst others, the card account number, PIN number, start and expiry dates. Some of this data, such as the account number, is essentially fixed. Security data may need to be altered occasionally by the user from a terminal. If the card is used as a cash card its credit will need to be charged via an ATM and discharged when payments are made. The size and cost sensitivities of a smart card processor is such that integral EEPROM data storage is highly advantageous.

Figure 15.1 shows the logic organization of the PIC16F8X EEPROM Data module.1 The memory matrix is not part of the normal Data and Program stores but is indirectly accessed via four SPRs which address the target byte, collect/hold data and control the read and write processes.

EEPROM matrix

The mid-range EEPROM Data module architecture supports 256 byte cells. The bottom 64 locations are implemented in both the PIC16F83 and PIC16F84 devices. The PIC16F873/4 has a capacity of 128 bytes and the PIC16F876/7 implement all 256 memory cells. Key features are:

1,000,000 minimum (107 typical) Erase/Write cycle endurance for each cell.

Maximum Erase/Write cycle time 8 ms.

Data retention greater than 40 years.

EEPROM ADdRess register EEADR

The EEADR register located at File 09h can address up to a maximum of 256 bytes of EEPROM data. Where less than maximum capacity is implemented, unused upper address bits must be 0 to ensure that the address is within the physical address space. In the PIC16F8X allowable addresses are in the range 00–3Fh.

EEPROM DATA register EEDATA

The EEDATA register located at File 08h either holds the 8-bit datum read out of the addressed cell or the byte the programmer wishes to write to the target EEPROM cell.

EEPROM CONtrol register 1 EECON1

The EEPROM module has two modes of operation, with EECON1 located at File 88h in Bank 1 controlling and monitoring the Read and Write cycles

– see Fig. 15.2.

1The earlier PIC16C83/4 had an identical architecture.


15. To Have and to Hold 433

6 EEIE INTCON h0B File

Interrupt on Write complete

EECON1

7

6

5

4

3

2

1

0

EEIF

WRERR

WREN

WR

RD

File 88h

(U 0)

(U 0)

(U 0)

(R/W 0)

(R/W X)

(R/W 0)

(R/S 0)

(R/S 0)

EEPROM CONtrol 2

Interlock

01010101 10101010

EECON2

File 89h

(Power-on reset) R = Readable bit W = Writable bit S = Settable bit

U= Unimplemented Read as 0

EEPROM

7

a

ADdRess

register

0

a

EEADR

h 09 File

Write

Read

Data EEPROM

64 bytes

d7 d0

EEPROM DATA register

EEDATA

File 08h

Fig. 15.1 The PIC16F8X Data EEPROM module.