Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

Figure 6.16

Circuit of example 6.12: (a) top-level diagram, (b) specifications provided, (c) implemented truth-table, and

(d) the right approach.

With respect to rule 2, however, the consequences can be more serious because incomplete specifications of the output signals might cause the synthesizer to infer latches in order to hold their previous values. This fact is illustrated in the example below.

Example 6.12: Bad Combinational Design

Let us consider the circuit of figure 6.16, for which the following specifications have been provided: x should behave as a multiplexer; that is, should be equal to the input selected by sel; y, on the other hand, should be equal to ‘0’ when sel ¼ ‘‘00’’, or ‘1’ if sel ¼ ‘‘01’’. These specifications are summarized in the truth-table of figure 6.16(b).

Notice that this is a combinational circuit. However, the specifications provided for y are incomplete, as can be observed in the truth-table of figure 6.16(b). Using just these specifications, the code could be the following:

1 --------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 --------------------------------------

5ENTITY example IS

6 PORT (a, b, c, d: IN STD_LOGIC; 7 sel: IN INTEGER RANGE 0 TO 3; 8 x, y: OUT STD_LOGIC);

9 END example;

10 --------------------------------------

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11 ARCHITECTURE example OF example IS

12BEGIN

13PROCESS (a, b, c, d, sel)

14BEGIN

15IF (sel=0) THEN

16x<=a;

17y<='0';

18ELSIF (sel=1) THEN

19x<=b;

20y<='1';

21ELSIF (sel=2) THEN

22x<=c;

23ELSE

24x<=d;

25END IF;

26END PROCESS;

27END example;

28--------------------------------------

After compiling this code, the report files show that no flip-flops were inferred (as expected). However, when we look at the simulation results (figure 6.17), we notice something peculiar about y. Observe that, for the same value of the input (sel ¼ 3 ¼ ‘‘11’’), two di¤erent results are obtained for y (when sel ¼ 3 is preceded by sel ¼ 0, y ¼ ‘0’ results, while y ¼ ‘1’ is obtained when sel ¼ 3 is preceded by sel ¼ 1). This signifies that some sort of memory was indeed implemented by the compiler. In fact, if we look at the equations obtained with Quartus II, for example (appendix D), we verify that y was computed as y ¼ (sel(0) AND sel(1)) OR (sel(0) AND y) OR

Figure 6.17

Simulation results of example 6.12.

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(sel(1) AND y). Therefore, a latch (using AND/OR gates) was implemented, which renders the truth-table of figure 6.16(c).

To avoid the extra logic required by the latch, the specifications of figure 6.16(d) should be used (‘X’ was used for all unknown or ‘‘don’t care’’ values). Thus the line y<='X'; must be included below lines 22 and 24 in the code above. Now, y can be as simple as y ¼ sel(0).

6.11Problems

Like the examples just seen, the purpose of the problems proposed in this section is to further illustrate the construction of sequential code (that is, the use of IF, WAIT, CASE, and LOOP, always inside a PROCESS). However, if you want to know more about SIGNALS and VARIABLES before working on the problems below, you may have a look at chapter 7, and then return to this section. Finally, recall that with sequential code we can implement sequential as well as combinational logic circuits. Though you will be using only sequential code in this section, you are invited to determine whether each circuit in the problems below (and in the examples just seen, for that matter) is actually a combinational or sequential circuit.

Problem 6.1: Event Counter

Design a circuit capable of counting the number of clock events (number of rising edges þ falling edges, figure P6.1).

Problem 6.2: Shift Register

Write a VHDL code that implements the 4-stage shift-register of figure P6.2. The solution should be di¤erent from that of example 6.3.

Problem 6.3: Priority Encoder

Figure P6.3 shows the same priority encoder of problem 5.2. The circuit must encode the address of the input bit of highest order that is active. The output ‘‘000’’ should indicate that there is no request at the input (no bit active). Write a VHDL solution for this circuit using only sequential code. Present two solutions:

clk

Figure P6.1

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Figure P6.4

(a)With IF.

(b)With CASE.

Problem 6.4: Generic Frequency Divider

Write a VHDL code for a circuit capable of dividing the frequency of an input clock signal by an integer n (figure P6.4). The code should be generic; that is, n should be defined using the GENERIC statement.

Problem 6.5: Frequency Multiplier

What about the opposite of problem 6.4, that is, say that we want to multiply the clock frequency by n. Can it be done?

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Problem 6.6: Timer #1

Design a timer capable of running from 0min:00sec to 9min:59sec (figure P6.6). The circuit must have start, stop, and reset buttons. The outputs must be SSD coded. Consider that a reliable 1 Hz clock signal is available.

Problem 6.7: Timer #2

Consider the timer of problem 6.6. However, say that now only one button is available, which must perform the start and stop functions alternately, and it also resets the circuit when pressed for more than 2 seconds. Write a VHDL code for such a timer (figure P6.7). Again, consider that a reliable 1 Hz clock is available.

Problem 6.8: Parity Detector

Figure P6.8 shows the top-level diagram of a parity detector. The input vector has eight bits. The output must be ‘0’ when the number of ‘1’s in the input vector is even, or ‘1’ otherwise. Write a sequential code for this circuit. If possible, write more than one solution.

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Problem 6.9: Count Ones

Say that we want to design a circuit that counts the number of ‘1’s in a given binary vector (table P6.9). Write a VHDL code that implements such a circuit. Then synthesize and test your solution.

Problem 6.10: Intensity Encoder

Design an encoder that receives as input a 7-bit vector din, and creates from it an output vector dout whose bits are all ‘0’s, except the bit whose index corresponds to the number of ‘1’s in din. All possible situations are summarized in table P6.10.

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Problem 6.11: Multiplexer

Write a sequential VHDL code for the circuit of problem 5.1. If possible, present more than one solution.

Problem 6.12: Vector Shifter

Write a sequential VHDL code for the circuit of example 5.6. If possible, present more than one solution.

Problem 6.13: ALU

Write a sequential VHDL code for the circuit of example 5.5. If possible, present more than one solution.

Problem 6.14: Signed/Unsigned Adder/Subtractor

Solve problem 5.5 using sequential code. Make the code as generic as possible.

Problem 6.15: Comparator

Solve problem 5.8 using sequential code.

Problem 6.16: Carry Ripple Adder

Consider the carry ripple adder of example 6.8.

(a)Why cannot we replace the IF statement of lines 17–19 in solution 2 by simply ‘‘temp:=c0;’’?

(b)Notice that the circuit of example 6.8 is fully combinational, so it can also be implemented using only concurrent code (that is, without a PROCESS). Write such a code for it. Then simulate it and analyze the results.

Problem 6.17: DFF

Consider the DFF with asynchronous reset of figure 6.1. Below are several codes for that circuit. Examine each of them and determine whether they should work properly. Briefly explain your answers.

--------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

--------------------------------------

ENTITY dff IS

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PORT ( d, clk, rst: IN BIT; q: OUT BIT);

END dff;

-----Solution 1 ---------------------

ARCHITECTURE arch1 OF dff IS BEGIN

PROCESS (clk, rst) BEGIN

IF (rst='1') THEN q <= '0';

ELSIF (clk'EVENT AND clk='1') THEN q <= d;

END IF; END PROCESS;

END arch1;

-----Solution 2 ---------------------

ARCHITECTURE arch2 OF dff IS BEGIN

PROCESS (clk) BEGIN

IF (rst='1') THEN q <= '0';

ELSIF (clk'EVENT AND clk='1') THEN q <= d;

END IF; END PROCESS;

END arch2;

-----Solution 3 ---------------------

ARCHITECTURE arch3 OF dff IS BEGIN

PROCESS (clk) BEGIN

IF (rst='1') THEN q <= '0';

ELSIF (clk'EVENT) THEN q <= d;

END IF; END PROCESS;

END arch3;

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-----Solution 4 ---------------------

ARCHITECTURE arch4 OF dff IS BEGIN

PROCESS (clk) BEGIN

IF (rst='1') THEN q <= '0';

ELSIF (clk='1') THEN q <= d;

END IF; END PROCESS;

END arch4;

-----Solution 5 ---------------------

ARCHITECTURE arch5 OF dff IS BEGIN

PROCESS (clk, rst, d) BEGIN

IF (rst='1') THEN q <= '0';

ELSIF (clk='1') THEN q <= d;

END IF; END PROCESS;

END arch5;

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