Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

1 ---- Solution 2: OK -------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------

5ENTITY dff IS

6PORT ( d, clk: IN STD_LOGIC;

7q: BUFFER STD_LOGIC;

12BEGIN

13PROCESS (clk)

14BEGIN

15IF (clk'EVENT AND clk='1') THEN

16q <= d;

17END IF;

18END PROCESS;

19qbar <= NOT q;

20END ok;

21 ---------------------------------------

Comments:

In solution 1, the assignments q<=d (line 16) and qbar<=NOT q (line 17) are both synchronous, so their new values will only be available at the conclusion of the PROCESS. This is a problem for qbar, because the new value of q has not propagated yet. Therefore, qbar will assume the reverse of the old value of q. In other words, the right value of qbar will be one clock cycle delayed, thus causing the circuit not to work correctly. This behavior can be observed in the upper graph of figure 7.5.

In solution 2, we have placed qbar<=NOT q (line 30) outside the PROCESS, thus operating as a true concurrent expression. The behavior of the resulting circuit can be observed in the lower graph of figure 7.5.

Example 7.5: Frequency Divider

In this example, we want to implement a circuit that divides the clock frequency by 6 (figure 7.6). Intentionally, we have implemented two outputs, one based on a SIGNAL (count1) and the other based on a VARIABLE (count2). Knowing that both work properly (see simulation results in figure 7.7), you are invited to fill in the two blanks and to explain your answers.

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Figure 7.5

Simulation results of example 7.4.

Figure 7.6

Frequency divider of example 7.5.

Figure 7.7

Simulation results of example 7.5.

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1 -----------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -----------------------------------------

5ENTITY freq_divider IS

6PORT ( clk : IN STD_LOGIC;

11SIGNAL count1 : INTEGER RANGE 0 TO 7;

12BEGIN

13PROCESS (clk)

14VARIABLE count2 : INTEGER RANGE 0 TO 7;

15BEGIN

16IF (clk'EVENT AND clk='1') THEN

17count1 <= count1 + 1;

18count2 := count2 + 1;

19IF (count1 = ? ) THEN

20out1 <= NOT out1;

21count1 <= 0;

22END IF;

23IF (count2 = ? ) THEN

24out2 <= NOT out2;

25count2 := 0;

26END IF;

27END IF;

28END PROCESS;

29END example;

30 -----------------------------------------

7.5Number of Registers

In this section, we will discuss the number of flip-flops inferred from the code by the compiler. The purpose is not only to understand which approaches require less registers, but also to make sure that the code does implement the expected circuit.

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A SIGNAL generates a flip-flop whenever an assignment is made at the transition of another signal; that is, when a synchronous assignment occurs. Such assignment, being synchronous, can only happen inside a PROCESS, FUNCTION, or PROCEDURE (usually following a declaration of the type ‘‘IF signal’EVENT . . .’’ or ‘‘WAIT UNTIL . . .’’).

A VARIABLE, on the other hand, will not necessarily generate flip-flops if its value never leaves the PROCESS (or FUNCTION, or PROCEDURE). However, if a value is assigned to a variable at the transition of another signal, and such value is eventually passed to a signal (which leaves the process), then flip-flops will be inferred. A VARIABLE also generates a register when it is used before a value has been assigned to it. The examples presented below will illustrate these points.

Example: In the process shown below, output1 and output2 will both be stored (that is, infer flip-flops), because both are assigned at the transition of another signal (clk).

PROCESS (clk)

BEGIN

IF (clk'EVENT AND clk='1') THEN

Example: In the next process, only output1 will be stored (output2 will make use of logic gates).

PROCESS (clk)

BEGIN

IF (clk'EVENT AND clk='1') THEN

Example: In the process below, temp (a variable) will cause x (a signal) to be stored.

PROCESS (clk)

VARIABLE temp: BIT;

BEGIN

IF (clk'EVENT AND clk='1') THEN

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Additional (complete) examples are presented next. The purpose is to further illustrate when and why registers are inferred from SIGNAL and VARIABLE assignments.

Example 7.6: DFF with q and qbar #2

Let us consider the DFF of figure 7.4 once again. Both solutions presented below function properly. The di¤erence between them, however, resides in the number of flip-flops needed in each case. Solution 1 has two synchronous SIGNAL assignments (lines 16–17), so 2 flip-flops will be generated. This is not the case in solution 2, where one of the assignments (line 19) is no longer synchronous. The resulting circuits are presented in figures 7.8(a)–(b), respectively.

1 ---- Solution 1: Two DFFs ---------------

2LIBRARY ieee;

3USE ieee.std_logic_1164.all;

4 -----------------------------------------

5ENTITY dff IS

6PORT ( d, clk: IN STD_LOGIC;

Figure 7.8

Circuits inferred from the code of example 7.6: (a) solution 1, (b) solution 2.

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7q: BUFFER STD_LOGIC;

12BEGIN

13PROCESS (clk)

14BEGIN

15IF (clk'EVENT AND clk='1') THEN

18END IF;

19END PROCESS;

20END two_dff;

21 -----------------------------------------

1 ---- Solution 2: One DFF ----------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -----------------------------------------

5ENTITY dff IS

6PORT ( d, clk: IN STD_LOGIC;

7q: BUFFER STD_LOGIC;

12BEGIN

13PROCESS (clk)

14BEGIN

15IF (clk'EVENT AND clk='1') THEN

17END IF;

18END PROCESS;

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rst

Figure 7.9

0-to-7 counter of example 7.7.

Comments:

Example 7.6 illustrates a very important situation, in which extra (unnecessary) hardware might be inferred when the code is not assembled carefully. With solution 2, the synthesizer will always infer only one flip-flop. It is interesting to mention, however, that for certain types of CPLD/FPGA devices, when the signals q and qbar are connected directly to chip pins, the fitter (place & route) might still opt for two flip-flops in the physical implementation. This does not mean that two flip-flops were indeed necessary. In fact, though the fitter (place & route) report might mention two registers in such cases, the synthesis report will invariably inform that only one register was indeed required. A further discussion is presented in problem 7.7.

Example 7.7: Counter

Let us consider the 0-to-7 counter of figure 7.9. Two solutions are presented below. In the first, a synchronous VARIABLE assignment is made (lines 14–15). In the second, a synchronous SIGNAL assignment occurs (lines 13–14).

From either solution, three flip-flops are inferred (to hold the 3-bit output signal count). Solution 1 is an example that a VARIABLE can indeed generate registers. The reason is that its assignment (line 15) is at the transition of another signal (clk, line 14) and its value does leave the PROCESS (line 17).

Solution 2, on the other hand, uses only SIGNALS. Notice that, since no auxiliary signal was used, count needed to be declared as of mode BUFFER (line 4), because it is assigned a value and is also read (used) internally (line 14). Still regarding line 14 of solution 2, notice that a SIGNAL, like a VARIABLE, can also be incremented when used in a sequential code. Finally, notice that neither in solution 1 nor in solution 2 was the std_logic_1164 package declared, because we are not using std_logic data types in this example.

1 ------ Solution 1: With a VARIABLE --------

2 ENTITY counter IS

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3PORT ( clk, rst: IN BIT;

7ARCHITECTURE counter OF counter IS

8BEGIN

9PROCESS (clk, rst)

10VARIABLE temp: INTEGER RANGE 0 TO 7;

11BEGIN

12IF (rst='1') THEN

13temp:=0;

14ELSIF (clk'EVENT AND clk='1') THEN

15temp := temp+1;

16END IF;

17count <= temp;

18END PROCESS;

19END counter;

20 --------------------------------------------

1 ------ Solution 2: With SIGNALS only -------

2ENTITY counter IS

3PORT ( clk, rst: IN BIT;

7ARCHITECTURE counter OF counter IS

8BEGIN

9PROCESS (clk, rst)

10BEGIN

11IF (rst='1') THEN

12count <= 0;

13ELSIF (clk'EVENT AND clk='1') THEN

14count <= count + 1;

15END IF;

16END PROCESS;

17END counter;

18 --------------------------------------------

Simulation results (from either solution above) are shown in figure 7.10.

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Example 7.8: Shift Register #1

We are now interested in examining what happens to the 4-stage shift register of figure 7.11 when di¤erent VARIABLE and SIGNAL assignments are made. Of course, if the solution is correct, then the output signal (dout) should be four positive clock edges behind the input signal (din).

In solution 1, three VARIABLES are used (a, b, and c, line 10). However, the variables are used before values are assigned to them (that is, in reverse order, starting with dout, line 13, and ending with din, line 16). Consequently, flip-flops will be inferred, which store the values from the previous run of the PROCESS.

In solution 2, the variables were replaced by SIGNALS (line 8), and the assignments are made in direct order (from din to dout, lines 13–16). Since signal assignments at the transition of another signal do generate registers, here too the right circuit will be inferred.

Finally, in solution 3, the same variables of solution 1 were employed, but in direct order (from din to dout, lines 13–16). Recall, however, that an assignment to a variable is immediate, and since the variables are being used in direct order (that is, after values have been assigned to them), lines 13–15 collapse into one line, equivalent to c :¼ din. The value of c does leave the process in the next line (line 16), however, where a signal assignment (dout <¼ c) occurs at the transition of clk. Therefore, one register will be inferred from solution 3, thus not resulting the correct circuit.

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Note: More conventional solutions to the shift-register problem will be presented in example 7.9.

2ENTITY shift IS

3PORT ( din, clk: IN BIT;

7ARCHITECTURE shift OF shift IS

8BEGIN

9PROCESS (clk)

10VARIABLE a, b, c: BIT;

11BEGIN

12IF (clk'EVENT AND clk='1') THEN

13dout <= c;

14c := b;

15b := a;

16a := din;

17END IF;

18END PROCESS;

19END shift;

2ENTITY shift IS

3PORT ( din, clk: IN BIT;

9BEGIN

10PROCESS (clk)

11BEGIN

12IF (clk'EVENT AND clk='1') THEN

13a <= din;

14b <= a;

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