Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

a)Complete the VHDL code below.

b)Write relevant comments regarding your solution (as in examples 2.1 and 2.2).

c)Compile and simulate your solution, checking whether it works as expected.

Note: A solution using IF was employed in the code below, because it is more intuitive. However, as will be seen later, a multiplexer can also be implemented with other statements, like WHEN or CASE.

1 ---------------------------------------

2LIBRARY ieee;

3 USE _________________________ ;

4 ---------------------------------------

5ENTITY mux IS

6PORT ( __ , __ : ___ STD_LOGIC_VECTOR (7 DOWNTO 0);

7sel : IN ____________________________ ;

12BEGIN

13PROCESS (a, b, ____ )

14BEGIN

15IF (sel = "00") THEN

16c <= "00000000";

17ELSIF (__________) THEN

18c <= a;

19_____ (sel = "10") THEN

20c <= __;

21ELSE

22c <= (OTHERS => '__');

23END ___ ;

24END _________ ;

25END _________ ;

26 ---------------------------------------

TLFeBOOK

b

c

Figure P2.2

Problem 2.2: Logic Gates

a)Write a VHDL code for the circuit of figure P2.2. Notice that it is purely combinational, so a PROCESS is not necessary. Write an expression for d using only logical operators (AND, OR, NAND, NOT, etc.).

b)Synthesize and simulate your circuit. After assuring that it works properly, open the report file and check the actual expression implemented by the compiler. Compare it with your expression.

TLFeBOOK

3Data Types

In order to write VHDL code e‰ciently, it is essential to know what data types are allowed, and how to specify and use them. In this chapter, all fundamental data types are described, with special emphasis on those that are synthesizable. Discussions on data compatibility and data conversion are also included.

3.1Pre-Defined Data Types

VHDL contains a series of pre-defined data types, specified through the IEEE 1076 and IEEE 1164 standards. More specifically, such data type definitions can be found in the following packages / libraries:

Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL data types.

Package std_logic_1164 of library ieee: Defines STD_LOGIC and STD_ULOGIC data types.

Package std_logic_arith of library ieee: Defines SIGNED and UNSIGNED data types, plus several data conversion functions, like conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), and conv_std_logic_vector(p, b).

Packages std_logic_signed and std_logic_unsigned of library ieee: Contain functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED, respectively.

All pre-defined data types (specified in the packages/libraries listed above) are described below.

BIT (and BIT_VECTOR): 2-level logic (‘0’, ‘1’).

Examples:

SIGNAL x: BIT;

-- x is declared as a one-digit signal of type BIT.

SIGNAL y: BIT_VECTOR (3 DOWNTO 0);

-- y is a 4-bit vector, with the leftmost bit being the MSB.

SIGNAL w: BIT_VECTOR (0 TO 7);

-- w is an 8-bit vector, with the rightmost bit being the MSB.

Based on the signals above, the following assignments would be legal (to assign a value to a signal, the ‘‘<¼’’ operator must be used):

TLFeBOOK

x <= '1';

--x is a single-bit signal (as specified above), whose value is

--'1'. Notice that single quotes (' ') are used for a single bit.

y <= "0111";

--y is a 4-bit signal (as specified above), whose value is "0111"

--(MSB='0'). Notice that double quotes (" ") are used for

--vectors.

w <= "01110001";

-- w is an 8-bit signal, whose value is "01110001" (MSB='1').

STD_LOGIC (and STD_LOGIC_VECTOR): 8-valued logic system introduced in the IEEE 1164 standard.

Examples:

SIGNAL x: STD_LOGIC;

-- x is declared as a one-digit (scalar) signal of type STD_LOGIC.

SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";

--y is declared as a 4-bit vector, with the leftmost bit being

--the MSB. The initial value (optional) of y is "0001". Notice

--that the ":=" operator is used to establish the initial value.

Most of the std_logic levels are intended for simulation only. However, ‘0’, ‘1’, and ‘Z’ are synthesizable with no restrictions. With respect to the ‘‘weak’’ values, they are resolved in favor of the ‘‘forcing’’ values in multiply-driven nodes (see table 3.1). Indeed, if any two std_logic signals are connected to the same node, then conflicting logic levels are automatically resolved according to table 3.1.

STD_ULOGIC (STD_ULOGIC_VECTOR): 9-level logic system introduced in the IEEE 1164 standard (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘–’). Indeed, the

TLFeBOOK

Table 3.1

Resolved logic system (STD_LOGIC).

STD_LOGIC system described above is a subtype of STD_ULOGIC. The latter includes an extra logic value, ‘U’, which stands for unresolved. Thus, contrary to STD_LOGIC, conflicting logic levels are not automatically resolved here, so output wires should never be connected together directly. However, if two output wires are never supposed to be connected together, this logic system can be used to detect design errors.

BOOLEAN: True, False.

INTEGER: 32-bit integers (from 2,147,483,647 to þ2,147,483,647).

NATURAL: Non-negative integers (from 0 to þ2,147,483,647).

REAL: Real numbers ranging from 1.0E38 to þ1.0E38. Not synthesizable.

Physical literals: Used to inform physical quantities, like time, voltage, etc. Useful in simulations. Not synthesizable.

Character literals: Single ASCII character or a string of such characters. Not synthesizable.

SIGNED and UNSIGNED: data types defined in the std_logic_arith package of the ieee library. They have the appearance of STD_LOGIC_VECTOR, but accept arithmetic operations, which are typical of INTEGER data types (SIGNED and UNSIGNED will be discussed in detail in section 3.6).

Examples:

TLFeBOOK

SIGNAL c: STD_LOGIC;

SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL e: INTEGER RANGE 0 TO 255;

3.2 User-Defined Data Types

VHDL also allows the user to define his/her own data types. Two categories of userdefined data types are shown below: integer and enumerated.

User-defined integer types:

TYPE integer IS RANGE -2147483647 TO +2147483647; -- This is indeed the pre-defined type INTEGER.

TYPE natural IS RANGE 0 TO +2147483647;

-- This is indeed the pre-defined type NATURAL.

TLFeBOOK