Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

248 Chapter 10

ALU constructed from three COMPONENTS.

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Figure 10.8

Simulation results of example 10.6.

12 -----------------------------------------

13 ARCHITECTURE arith_unit OF arith_unit IS

14SIGNAL arith, logic: STD_LOGIC_VECTOR (7 DOWNTO 0);

15BEGIN

16WITH sel SELECT

17x <= a WHEN "000",

18a+1 WHEN "001",

19a-1 WHEN "010",

20b WHEN "011",

21b+1 WHEN "100",

22b-1 WHEN "101",

23a+b WHEN "110",

24a+b+cin WHEN OTHERS;

25END arith_unit;

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -----------------------------------------

5ENTITY logic_unit IS

6PORT ( a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

7sel: IN STD_LOGIC_VECTOR (2 DOWNTO 0);

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13WITH sel SELECT

14x <= NOT a WHEN "000",

15NOT b WHEN "001",

16a AND b WHEN "010",

17a OR b WHEN "011",

18a NAND b WHEN "100",

19a NOR b WHEN "101",

20a XOR b WHEN "110",

21NOT (a XOR b) WHEN OTHERS;

22END logic_unit;

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -----------------------------------------

5ENTITY mux IS

6PORT ( a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

7sel: IN STD_LOGIC;

12BEGIN

13WITH sel SELECT

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -----------------------------------------

5ENTITY alu IS

6PORT ( a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

7cin: IN STD_LOGIC;

8sel: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

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10 END alu;

11 -----------------------------------------

12 ARCHITECTURE alu OF alu IS

13 -----------------------

14COMPONENT arith_unit IS

15PORT ( a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

16cin: IN STD_LOGIC;

17sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

18x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

19END COMPONENT;

20 -----------------------

21COMPONENT logic_unit IS

22PORT ( a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

23sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

24x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

25END COMPONENT;

26 -----------------------

27COMPONENT mux IS

28PORT ( a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

29sel: IN STD_LOGIC;

30x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

31END COMPONENT;

32 -----------------------

33 SIGNAL x1, x2: STD_LOGIC_VECTOR(7 DOWNTO 0); 34 -----------------------

35BEGIN

36U1: arith_unit PORT MAP (a, b, cin, sel(2 DOWNTO 0), x1);

37U2: logic_unit PORT MAP (a, b, sel(2 DOWNTO 0), x2);

38U3: mux PORT MAP (x1, x2, sel(3), y);

39END alu;

40 ---------------------------------------------------

10.6Problems

Problem 10.1: ALU with Components Declared in a Package

Redo example 10.6. This time, create a PACKAGE containing all COMPONENT declarations. Then make the changes needed in the main code and recompile it. Synthesize and simulate your solution to fully verify its functionality.

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Problem 10.2: Carry Ripple Adder Constructed From Components

Consider the carry ripple adder discussed in section 9.3 (figure 9.6). Design a FAU (full adder unit), to be used as a COMPONENT. Compile it into the work LIBRARY. Then write a code for the complete carry ripple adder containing instantiations of FAU. Compile your project and simulate the synthesized circuit, comparing the results with those obtained in section 9.3.

Problem 10.3: Carry Look Ahead Adder Constructed from Components

Consider now the carry look ahead adder of section 9.3 (figure 9.8). Design a PGU (propagate-generate unit) and a CLAU (carry look ahead unit), to be used as COMPONENTS. Compile them into the work LIBRARY. Then write a code for the complete carry look ahead adder containing instantiations of PGU and CLAU. You can choose whether to declare the COMPONENTS in a specific PACKAGE or in the main code itself (in the declarative part of the ARCHITECTURE). Compile your project and simulate the synthesized circuit, comparing the results with those obtained in section 9.3.

Problem 10.4: Registered Counter

Figure P10.4 illustrates the construction of a hierarchical design. Two sub-circuits (that is, ‘‘components’’), called counter and register, are used to construct a higherlevel circuit, called stop_watch. The system consists of a free-running counter, which is reset every time the stop input is asserted. The status of the counter must be stored in the sub-circuit register just before reset occurs. Once stop returns to ‘0’, the counter resumes counting (from zero), while the register holds the previous count. Design the two components of figure P10.4, then instantiate them in the main code to produce the complete stop_watch circuit.

stop

Figure P10.4

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11Functions and Procedures

FUNCTIONS and PROCEDURES are collectively called subprograms. From a construction point of view, they are very similar to a PROCESS (studied in chapter 6), for they are the only pieces of sequential VHDL code, and thus employ the same sequential statements seen there (IF, CASE, and LOOP; WAIT is not allowed). However, from the applications point of view, there is a fundamental di¤erence between a PROCESS and a FUNCTION or PROCEDURE. While the first is intended for immediate use in the main code, the others are intended mainly for LIBRARY allocation, that is, their purpose is to store commonly used pieces of code, so they can be reused or shared by other projects. Nevertheless, if desired, a FUNCTION or PROCEDURE can also be installed in the main code itself.

11.1FUNCTION

A FUNCTION is a section of sequential code. Its purpose is to create new functions to deal with commonly encountered problems, like data type conversions, logical operations, arithmetic computations, and new operators and attributes. By writing such code as a FUNCTION, it can be shared and reused, also propitiating the main code to be shorter and easier to understand.

As already mentioned, a FUNCTION is very similar to a PROCESS (section 6.1). The same statements that can be used in a process (IF, WAIT, CASE, and LOOP) can also be used in a function, with the exception of WAIT. Other two prohibitions in a function are SIGNAL declarations and COMPONENT instantiations.

To construct and use a function, two parts are necessary: the function itself (function body) and a call to the function. Their syntaxes are shown below.

Function Body

FUNCTION function_name [<parameter list>] RETURN data_type IS [declarations]

BEGIN

(sequential statements) END function_name;

In the syntax above, 3parameter list4 specifies the function’s input parameters, that is:

3parameter list4 ¼ [CONSTANT] constant_name: constant_type; or

3parameter list4 ¼ SIGNAL signal_name: signal_type;

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There can be any number of such parameters (even zero), which, as shown above, can only be CONSTANT (default) or SIGNAL (VARIABLES are not allowed). Their types can be any of the synthesizable data types studied in chapter 3 (BOOLEAN, STD_LOGIC, INTEGER, etc.). However, no range specification should be included (for example, do not enter RANGE when using INTEGER, or TO/ DOWNTO when using STD_LOGIC_VECTOR). On the other hand, there is only one return value, whose type is specified by data_type.

Example: The function below, named f1, receives three parameters (a, b, and c). a and b are CONSTANTS (notice that the word CONSTANT can be omitted, for it is the default object), while c is a SIGNAL. a and b are of type INTEGER, while c is of type STD_LOGIC_VECTOR. Notice that neither RANGE nor DOWNTO was specified. The output parameter (there can be only one) is of type BOOLEAN.

FUNCTION f1 (a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR)

RETURN BOOLEAN IS

BEGIN

(sequential statements)

END f1;

Function Call

A function is called as part of an expression. The expression can obviously appear by itself or associated to a statement (either concurrent or sequential).

Examples of function calls:

Example 11.1: Function positive_edge( )

The FUNCTION below detects a positive (rising) clock edge. It is similar to the IF(clk’EVENT and clk ¼ ‘1’) statement. This function could be used, for example, in the implementation of a DFF.

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