Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

Figure 10.2

Basic ways of declaring COMPONENTS: (a) declarations in the main code itself, (b) declarations in a PACKAGE.

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a

x

b

Figure 10.3

Circuit of example 10.3.

10BEGIN

11c <= NOT (a AND b);

12END nand_2;

13 ---------------------------------------------

1----- File nand_3.vhd: ----------------------

2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ------------------------------------

5 ENTITY nand_3 IS

6 PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC); 7 END nand_3;

8 ------------------------------------

9 ARCHITECTURE nand_3 OF nand_3 IS 10 BEGIN

11 d <= NOT (a AND b AND c);

12 END nand_3;

13 ---------------------------------------------

1----- File project.vhd: ---------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ------------------------------------

5ENTITY project IS

6PORT (a, b, c, d: IN STD_LOGIC;

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10 ARCHITECTURE structural OF project IS

11 -------------

12COMPONENT inverter IS

13PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);

14END COMPONENT;

15 -------------

16COMPONENT nand_2 IS

17PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC);

18END COMPONENT;

19 -------------

20COMPONENT nand_3 IS

21PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC);

22END COMPONENT;

23 -------------

24SIGNAL w: STD_LOGIC;

25BEGIN

26U1: inverter PORT MAP (b, w);

27U2: nand_2 PORT MAP (a, b, x);

28U3: nand_3 PORT MAP (w, c, d, y);

29END structural;

30 ---------------------------------------------

Example 10.4: Components Declared in a Package

We want to implement the same project of the previous example (figure 10.3). However, we will now create a PACKAGE where all the COMPONENTS (inverter, nand_2, and nand_3) will be declared, like in figure 10.2(b). Thus now five pieces of VHDL code are needed: one for each component, one for the PACKAGE, and finally one for the project. Despite having an extra file (PACKAGE), such extra file needs to be created only once, thus avoiding the need to declare the components in the main code every time they are instantiated.

Notice that an extra USE clause (USE work.my_components.all) is now necessary, in order to make the PACKAGE my_components visible to the design. The simulation results are obviously the same as those of figure 10.4.

1 ------ File inverter.vhd: -------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ------------------------------------

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Figure 10.4

Experimental results of example 10.3.

5ENTITY inverter IS

6 PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); 7 END inverter;

8 ------------------------------------

9 ARCHITECTURE inverter OF inverter IS

10BEGIN

11b <= NOT a;

12END inverter;

13---------------------------------------------

1------ File nand_2.vhd: ---------------------

2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ------------------------------------

5 ENTITY nand_2 IS

6 PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC); 7 END nand_2;

8 ------------------------------------

9 ARCHITECTURE nand_2 OF nand_2 IS 10 BEGIN

11 c <= NOT (a AND b);

12 END nand_2;

13 ---------------------------------------------

1----- File nand_3.vhd: ----------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ------------------------------------

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5ENTITY nand_3 IS

6 PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC); 7 END nand_3;

8 ------------------------------------

9 ARCHITECTURE nand_3 OF nand_3 IS

10BEGIN

11d <= NOT (a AND b AND c);

12END nand_3;

13 ---------------------------------------------

1 ----- File my_components.vhd: ---------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ------------------------

5PACKAGE my_components IS

7COMPONENT inverter IS

8 PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);

9END COMPONENT;

10------ 2-input nand: ---

11COMPONENT nand_2 IS

12PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC);

13END COMPONENT;

14------ 3-input nand: ---

15COMPONENT nand_3 IS

16PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC);

17END COMPONENT;

18 ------------------------

19 END my_components;

20 ---------------------------------------------

1 ----- File project.vhd: ---------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE work.my_components.all;

5 ---------------------------------

6ENTITY project IS

7PORT ( a, b, c, d: IN STD_LOGIC;

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9END project;

10---------------------------------

11ARCHITECTURE structural OF project IS

12SIGNAL w: STD_LOGIC;

13BEGIN

14U1: inverter PORT MAP (b, w);

15U2: nand_2 PORT MAP (a, b, x);

16U3: nand_3 PORT MAP (w, c, d, y);

17END structural;

18---------------------------------------------

10.4 PORT MAP

There are two ways to map the PORTS of a COMPONENT during its instantiation: positional mapping and nominal mapping. Let us consider the following example:

COMPONENT inverter IS

PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);

END COMPONENT;

...

U1: inverter PORT MAP (x, y);

In it, the mapping is positional; that is, PORTS x and y correspond to a and b, respectively. On the other hand, a nominal mapping would be the following:

U1: inverter PORT MAP (x=>a, y=>b);

Positional mapping is easier to write, but nominal mapping is less error-prone. Ports can also be left unconnected (using the keyword OPEN). For example:

U2: my_circuit PORT MAP (x=>a, y=>b, w=>OPEN, z=>d);

10.5 GENERIC MAP

GENERIC units (discussed in section 4.5) can also be instantiated. In that case, a GENERIC MAP must be used in the COMPONENT instantiation to pass information to the GENERIC parameters. The new syntax is shown below.

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Figure 10.5

Generic parity generator to be instantiated in example 10.5.

label: compon_name GENERIC MAP (param. list) PORT MAP (port list);

As can be seen, the only di¤erences from the syntax already presented are the inclusion of the word GENERIC and of a parameter list. The purpose is to inform that those parameters are to be considered as generic. The usage of GENERIC MAP is illustrated in the example below.

Example 10.5: Instantiating a Generic Component

Let us consider the generic parity generator of example 4.3 (repeated in figure 10.5), which adds one bit to the input vector (on its left-hand side). Such bit must be a ‘0’ if the number of ‘1’s in the input vector is even, or a ‘1’ if it is odd, such that the resulting vector will always contain an even number of ‘1’s.

The code presented below is generic (that is, works for any positive integer n). Two files are shown: one relative to the COMPONENT (par_generator, which, indeed, we can assume as previously designed and available in the work library), and one relative to the project itself (main code), where the component par_generator is instantiated.

Notice that the default value (n ¼ 7) of GENERIC in the COMPONENT file (parity_gen) will be overwritten by the value n ¼ 2 passed to it by means of the GENERIC MAP statement in the COMPONENT instantiation. Notice also that the GENERIC declaration that appears along with the COMPONENT declaration in the second file is necessary, for it is part of the original (the component’s) ENTITY. However, it is not necessary to declare its default value again. Simulation results from the circuit synthesized with the code below are shown in figure 10.6.

1 ------ File parity_gen.vhd (component): -------------

2LIBRARY ieee;

3USE ieee.std_logic_1164.all;

4-----------------------------------

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Figure 10.6

Simulation results of example 10.5.

5ENTITY parity_gen IS

6 GENERIC (n : INTEGER := 7); -- default is 7

7PORT ( input: IN BIT_VECTOR (n DOWNTO 0);

12BEGIN

13PROCESS (input)

14VARIABLE temp1: BIT;

15VARIABLE temp2: BIT_VECTOR (output'RANGE);

16BEGIN

17temp1 := '0';

18FOR i IN input'RANGE LOOP

19temp1 := temp1 XOR input(i);

20temp2(i) := input(i);

21END LOOP;

22temp2(output'HIGH) := temp1;

23output <= temp2;

24END PROCESS;

25END parity;

26 ------------------------------------------------------

1 ------ File my_code.vhd (actual project): ------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -----------------------------------

5ENTITY my_code IS

6 GENERIC (n : POSITIVE := 2); -- 2 will overwrite 7 7 PORT ( inp: IN BIT_VECTOR (n DOWNTO 0);

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13COMPONENT parity_gen IS

14GENERIC (n : POSITIVE);

15PORT (input: IN BIT_VECTOR (n DOWNTO 0);

16output: OUT BIT_VECTOR (n+1 DOWNTO 0));

17END COMPONENT;

18 ------------------------

19BEGIN

20C1: parity_gen GENERIC MAP(n) PORT MAP(inp, outp);

21END my_arch;

22 ------------------------------------------------------

Example 10.6: ALU Made of COMPONENTS

In example 5.5, the design of an ALU (Arithmetic Logic Unit) was presented (diagram repeated in figure 10.7). In that example, the code was self-contained (that is, no external COMPONENT, FUNCTION, or PROCEDURE was called). In the present example, however, we will assume that our library contains the three components (logic_unit, arith_unit, and mux) with which the ALU can be constructed.

In the code shown below, besides the main code (alu.vhd), we have also included the design of the three components mentioned above. As can be seen, the COMPONENTS were declared in the main code itself. Simulation results are shown in figure 10.8, which are similar to those of example 5.5.

2LIBRARY ieee;

3USE ieee.std_logic_1164.all;

4 USE ieee.std_logic_unsigned.all;

5 -----------------------------------------

6ENTITY arith_unit IS

7PORT ( a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

8sel: IN STD_LOGIC_VECTOR (2 DOWNTO 0);

9cin: IN STD_LOGIC;

10x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));

11END arith_unit;

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