Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

12 Additional System Designs

In this chapter, additional designs are presented, with the purpose of further illustrating the usage of the VHDL units that are intended for system-level design: PACKAGES, COMPONENTS, FUNCTIONS, and PROCEDURES.

12.1Serial-Parallel Multiplier

Figure 12.1 shows the RTL diagram of a serial-parallel multiplier. One of the input vectors (a) is applied serially to the circuit (one bit at a time, starting from the LSB), while the other (b) is applied in parallel (all bits simultaneously). Say that a has M bits, while b has N. Then, after all M bits of a have been presented to the system, a string of M ‘0’s must follow, in order to complete the (M þ N)-bit output product.

As can be seen in figure 12.1, the system is pipelined, and is constructed using AND gates, full-adder units, plus registers (flip-flops). Each unit of the pipeline (except the leftmost one) requires one adder and two registers, plus an AND gate to compute one of the inputs. Thus for an M N multiplier, O(N) of such units are required.

The solution presented below is of structural type (only COMPONENTS were used). Notice that there is more than one level of instantiation (the unit called pipe instantiates other components, while in the final code, pipe is instantiated as well (besides other components).

The design of each component is shown below, along with the PACKAGE containing all COMPONENT declarations, followed by the project proper (main code). Simulation results were also included.

1 ------ and_2.vhd (component): ---------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------

5ENTITY and_2 IS

6PORT ( a, b: IN STD_LOGIC;

11BEGIN

12y <= a AND b;

13END and_2;

14 ---------------------------------------

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Figure 12.1

Serial-parallel multiplier.

1 ------ reg.vhd (component): -----------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------

5ENTITY reg IS

6PORT ( d, clk, rst: IN STD_LOGIC;

11BEGIN

12PROCESS (clk, rst)

13BEGIN

14IF (rst='1') THEN q<='0';

15ELSIF (clk'EVENT AND clk='1') THEN q<=d;

16END IF;

17END PROCESS;

18END reg;

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------

5 ENTITY fau IS

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6PORT ( a, b, cin: IN STD_LOGIC;

11BEGIN

12s <= a XOR b XOR cin;

13cout <= (a AND b) OR (a AND cin) OR (b AND cin);

14END fau;

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE work.my_components.all;

5 ---------------------------------------

6ENTITY pipe IS

7PORT ( a, b, clk, rst: IN STD_LOGIC;

12SIGNAL s, cin, cout: STD_LOGIC;

13BEGIN

14U1: COMPONENT fau PORT MAP (a, b, cin, s, cout);

15U2: COMPONENT reg PORT MAP (cout, clk, rst, cin);

16U3: COMPONENT reg PORT MAP (s, clk, rst, q);

17END structural;

18 ---------------------------------------

1----- my_components.vhd (package):-----

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------

5 PACKAGE my_components IS

6 --------------------------

7COMPONENT and_2 IS

8 PORT (a, b: IN STD_LOGIC; y: OUT STD_LOGIC);

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9 END COMPONENT;

10 --------------------------

11 COMPONENT fau IS

12PORT (a, b, cin: IN STD_LOGIC; s, cout: OUT STD_LOGIC);

13END COMPONENT;

14 --------------------------

15 COMPONENT reg IS

16PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC);

17END COMPONENT;

18 --------------------------

19 COMPONENT pipe IS

20PORT (a, b, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC);

21END COMPONENT;

22 --------------------------

23 END my_components;

24 ---------------------------------------

1 ----- multiplier.vhd (project): -------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE work.my_components.all;

5 ---------------------------------------

6ENTITY multiplier IS

7PORT ( a, clk, rst: IN STD_LOGIC;

8b: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

13SIGNAL and_out, reg_out: STD_LOGIC_VECTOR (3 DOWNTO 0);

14BEGIN

15U1: COMPONENT and_2 PORT MAP (a, b(3), and_out(3));

16U2: COMPONENT and_2 PORT MAP (a, b(2), and_out(2));

17U3: COMPONENT and_2 PORT MAP (a, b(1), and_out(1));

18U4: COMPONENT and_2 PORT MAP (a, b(0), and_out(0));

19U5: COMPONENT reg PORT MAP (and_out(3), clk, rst,

20reg_out(3));

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Figure 12.2

Simulation results of serial-parallel multiplier.

21U6: COMPONENT pipe PORT MAP (and_out(2), reg_out(3),

22clk, rst, reg_out(2));

23U7: COMPONENT pipe PORT MAP (and_out(1), reg_out(2),

24clk, rst, reg_out(1));

25U8: COMPONENT pipe PORT MAP (and_out(0), reg_out(1),

26clk, rst, reg_out(0));

27prod <= reg_out(0);

28END structural;

29---------------------------------------

Simulation results are shown in figure 12.2. a ¼ ‘‘1100’’ (decimal 12) was applied to the serial input. Notice that this input must start with the LSB (a(0) ¼ ‘0’), which appears in the time slot 100 ns–200 ns, while the MSB (a(3) ¼ ‘1’) is situated in 400 ns–500 ns. Recall that four zeros must then follow. On the other hand, at the parallel input, b ¼ ‘‘1101’’ (decimal 13) was applied. The expected result, prod ¼ ‘‘10011100’’ (decimal 156), can be observed in the lower plot. Recall that the first bit out is the LSB; that is, prod(0) ¼ ‘0’, which appears in the time slot immediately after the first rising edge of clock; (that is, 150 ns–250 ns), while the last bit (MSB) of prod is situated in 850 ns–950 ns.

12.2Parallel Multiplier

Figure 12.3 shows the diagram of a 4-bit parallel multiplier. Contrary to the case of figure 12.1, here all input bits are applied to the system simultaneously. Therefore, registers are not required. Notice in figure 12.3 that only AND gates and FAU (full adder units) are necessary to construct a parallel multiplier. The operands are a and b (each of four bits), and the resulting product is prod (eight bits).

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Figure 12.3

Parallel multiplier.

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Figure 12.4

Simulation results of parallel multiplier.

The VHDL code shown below was based on COMPONENT instantiation. Notice that two basic components, AND_2 and FAU, were first specified (shown in section 12.1). These components were then instantiated to construct higher-level components, top_row, mid_row, and lower_row. All of these components were then declared in a PACKAGE called my_components, and finally used in the project called multiplier to implement the circuit of figure 12.3. Simulation results are shown in figure 12.4.

1 ------- top_row.vhd (component): -------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE work.my_components.all;

5 ---------------------------------------

6ENTITY top_row IS

7PORT ( a: IN STD_LOGIC;

8b: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

9sout, cout: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);

10p: OUT STD_LOGIC);

11END top_row;

12 ---------------------------------------

13 ARCHITECTURE structural OF top_row IS

14BEGIN

15U1: COMPONENT and_2 PORT MAP (a, b(3), sout(2));

16U2: COMPONENT and_2 PORT MAP (a, b(2), sout(1));

17U3: COMPONENT and_2 PORT MAP (a, b(1), sout(0));

18U4: COMPONENT and_2 PORT MAP (a, b(0), p);

19cout(2)<='0'; cout(1)<='0'; cout(0)<='0';

20END structural;

21 ----------------------------------------------

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1 ------- mid_row.vhd (component): -------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE work.my_components.all;

5 ---------------------------------------

6ENTITY mid_row IS

7PORT ( a: IN STD_LOGIC;

8b: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

9sin, cin: IN STD_LOGIC_VECTOR (2 DOWNTO 0);

10sout, cout: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);

11p: OUT STD_LOGIC);

12END mid_row;

13 ---------------------------------------

14 ARCHITECTURE structural OF mid_row IS

15SIGNAL and_out: STD_LOGIC_VECTOR (2 DOWNTO 0);

16BEGIN

17U1: COMPONENT and_2 PORT MAP (a, b(3), sout(2));

18U2: COMPONENT and_2 PORT MAP (a, b(2), and_out(2));

19U3: COMPONENT and_2 PORT MAP (a, b(1), and_out(1));

20U4: COMPONENT and_2 PORT MAP (a, b(0), and_out(0));

21U5: COMPONENT fau PORT MAP (sin(2), cin(2), and_out(2),

22sout(1), cout(2));

23U6: COMPONENT fau PORT MAP (sin(1), cin(1), and_out(1),

24sout(0), cout(1));

25U7: COMPONENT fau PORT MAP (sin(0), cin(0), and_out(0),

26p, cout(0));

27END structural;

28 ----------------------------------------------

1 ------- lower_row.vhd (component): -----------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE work.my_components.all;

5 ---------------------------------------

6ENTITY lower_row IS

7PORT ( sin, cin: IN STD_LOGIC_VECTOR (2 DOWNTO 0);

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11 ARCHITECTURE structural OF lower_row IS

12SIGNAL local: STD_LOGIC_VECTOR (2 DOWNTO 0);

13BEGIN

14local(0)<='0';

15U1: COMPONENT fau PORT MAP (sin(0), cin(0), local(0),

16p(0), local(1));

17U2: COMPONENT fau PORT MAP (sin(1), cin(1), local(1),

18p(1), local(2));

19U3: COMPONENT fau PORT MAP (sin(2), cin(2), local(2),

20p(2), p(3));

21END structural;

22 ----------------------------------------------

1 ----- my_components.vhd (package): -----------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ------------------------------------

5 PACKAGE my_components IS

6 -----------------------

7COMPONENT and_2 IS

12PORT ( a, b, cin: IN STD_LOGIC; s, cout: OUT STD_LOGIC);

13END COMPONENT;

14 -----------------------

15COMPONENT top_row IS

16PORT ( a: IN STD_LOGIC;

22COMPONENT mid_row IS

23PORT ( a: IN STD_LOGIC;

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