Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

30COMPONENT lower_row IS

31PORT ( sin, cin: IN STD_LOGIC_VECTOR (2 DOWNTO 0);

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE work.my_components.all;

5 ---------------------------------------

6ENTITY multiplier IS

7PORT ( a, b: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

12TYPE matrix IS ARRAY (0 TO 3) OF

13STD_LOGIC_VECTOR (2 DOWNTO 0);

14SIGNAL s, c: matrix;

15BEGIN

16U1: COMPONENT top_row PORT MAP (a(0), b, s(0), c(0),

17prod(0));

18U2: COMPONENT mid_row PORT MAP (a(1), b, s(0), c(0), s(1),

19c(1), prod(1));

20U3: COMPONENT mid_row PORT MAP (a(2), b, s(1), c(1), s(2),

21c(2), prod(2));

22U4: COMPONENT mid_row PORT MAP (a(3), b, s(2), c(2), s(3),

23c(3), prod(3));

24U5: COMPONENT lower_row PORT MAP (s(3), c(3),

25prod(7 DOWNTO 4));

26END structural;

27 ----------------------------------------------

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Figure 12.5

Parallel multiplier inferred from the pre-defined ‘‘*’’ operator.

A Simpler Approach

The example above had the purpose of exploring several aspects related to system design using VHDL. However, for the particular case of a parallel multiplier, it can be immediately inferred by means of the pre-defined ‘‘*’’ (multiplication) operator. Therefore, the circuit above can be represented using the compact form of figure 12.5, and the whole code above can be replaced by the following code:

1 ---------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE ieee.std_logic_arith.all;

5 ---------------------------------------

6ENTITY multiplier3 IS

7PORT ( a, b: IN SIGNED(3 DOWNTO 0);

12BEGIN

13prod <= a * b;

14END behavior;

15 ---------------------------------------

12.3Multiply-Accumulate Circuits

Multiplication followed by accumulation is a common operation in many digital systems, particularly those highly interconnected, like digital filters, neural networks, data quantizers, etc.

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Figure 12.6

MAC circuit.

One typical MAC (multiply-accumulate) architecture is illustrated in figure 12.6. It consists of multiplying two values, then adding the result to the previously accumulated value, which must then be re-stored in the registers for future accumulations. Another feature of a MAC circuit is that it must check for overflow, which might happen when the number of MAC operations is large.

This design can be done using COMPONENTS, because we have already designed each of the units shown in figure 12.6. However, since it is a relatively simple circuit, it can also be designed directly. The latter approach is illustrated below, while the former is treated in problem 12.2. In any case, the MAC circuit, as a whole, can be used as a COMPONENT in applications like digital filters and neural networks (next sections).

Overflow: In the implementation (code) shown below, a FUNCTION was written to detect overflow and truncate the result in case overflow happens. Overflow in a signed adder occurs when two operands with the same signal (leftmost bit) produce a result with a di¤erent signal from them. If it occurs, the largest value (positive or negative) should be assigned to the result. For example, if eight bits are used to encode the values, the addition of two positive numbers must fall in the interval from 0 to 127, while the addition of two negative numbers must fall between 128 (that is, þ128 in unsigned representation) and 1 (255 in unsigned representation). For example, 65 þ 65 ¼ 130, which is indeed 126 (overflow), so the result should be truncated to the largest positive value (127). Likewise, ( 70) þ ( 70) ¼ 140, which is, indeed, 116 (overflow), so the result should be truncated to the most negative value ( 128). On the other hand, when the operands have di¤erent signals, overflow cannot happen.

The add_truncate( ) function was placed in a PACKAGE (chapter 10) called my_functions. The function receives two signals, adds them, then checks for overflow

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and truncates the result if necessary, returning the processed result to the main code. Notice that the function is generic, for the number of bits of the operands is passed to it by means of a parameter called size. Notice also in the main code that the parameters passed to the function were declared as signals (line 14), because variables are not allowed (chapter 11).

1 ------- PACKAGE my_functions: -----------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE ieee.std_logic_arith.all;

5 ----------------------------------------------------------

6PACKAGE my_functions IS

7 FUNCTION add_truncate (SIGNAL a, b: SIGNED; size: INTEGER) 8 RETURN SIGNED;

9 END my_functions;

10 ----------------------------------------------------------

11 PACKAGE BODY my_functions IS

12FUNCTION add_truncate (SIGNAL a, b: SIGNED; size: INTEGER)

13RETURN SIGNED IS

14VARIABLE result: SIGNED (7 DOWNTO 0);

15BEGIN

16result := a + b;

17IF (a(a'left)=b(b'left)) AND

18(result(result'LEFT)/=a(a'left)) THEN

19result := (result'LEFT => a(a'LEFT),

21END IF;

22RETURN result;

23END add_truncate;

24END my_functions;

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE ieee.std_logic_arith.all;

5 USE work.my_functions.all;

6 ------------------------------------------

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7ENTITY mac IS

8PORT ( a, b: IN SIGNED(3 DOWNTO 0);

9clk, rst: IN STD_LOGIC;

10acc: OUT SIGNED(7 DOWNTO 0));

11END mac;

12------------------------------------------

13ARCHITECTURE rtl OF mac IS

14SIGNAL prod, reg: SIGNED(7 DOWNTO 0);

15BEGIN

16PROCESS (rst, clk)

17VARIABLE sum: SIGNED(7 DOWNTO 0);

18BEGIN

19prod <= a * b;

20IF (rst='1') THEN

21reg <= (OTHERS=>'0');

22ELSIF (clk'EVENT AND clk='1') THEN

23sum := add_truncate (prod, reg, 8);

24reg <= sum;

25END IF;

26acc <= reg;

27END PROCESS;

28END rtl;

29------------------------------------------

Simulation results are presented in figure 12.7. Notice that the following sequence of signals was presented to the MAC circuit: a ¼ (0, 2, 4, 6, 8, 6, 4, 2), b ¼ (0, 3, 6, 7, 8, 8, 8). Therefore, the expected output sequence is acc ¼ (0, 6, 30,12, 52, 100, 148) (recall that 12 is represented in the graph as 256 12 ¼ 244).

Figure 12.7

Simulation results of MAC circuit.

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All the values are OK, except the last one, for it is above the maximum positive value allowed for 8-bit signed numbers (127). Therefore, this result was kept at 127.

12.4Digital Filters

Digital signal processing (DSP) finds innumerable applications in the fields of audio, video, and communications, among others. Such applications are generally based on LTI (linear time invariant) systems, which can be implemented with digital circuitry.

Any LTI system be represented by the following equation:

NM

where ak and bk are the filter coe‰cients, and x[n k], y[n k] are the current (for k ¼ 0) and earlier (for k > 0) input and output values, respectively. To implement this expression, registers are necessary to store x[n k] and/or y[n k] (for k > 0), besides multipliers and adders, which are well-known building blocks in the digital domain.

The impulse response of a digital filter can be divided into two categories: IIR (infinite impulse response) and FIR (finite impulse response). The former corresponds to the general case described by the equation above, while the latter occurs when N ¼ 0. Only FIR filters can exhibit linear phase, so they are indispensable when linear phase is required, like in many telecom applications. With N ¼ 0, the equation above becomes

M

y[n] ¼ ckx[n k]

k¼0

where ck ¼ bk/a0 are the coe‰cients of the FIR filter. This equation can be implemented by the system of figure 12.8, where D (delay) represents a register (flip-flops), a triangle is a multiplier, and a circle means an adder.

An equivalent RTL representation is shown in figure 12.9. As shown, the values of x are stored in a shift register, whose outputs are connected to multipliers and then to adders. The coe‰cients must also be stored on chip. However, if the coe‰cients are always the same (that is, if it is a dedicated filter), their values can be implemented by means of logic gates rather than registers (we just need to store CONSTANTS). On the other hand, if it is a general purpose filter, then registers are required for the coe‰cients. In the architecture of figure 12.9, the output vector (y) was also stored, in order to provide a clean, synchronous output.

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c1

D

x[n-2] + c2

D

x[n-3]

c3

Figure 12.8

FIR filter diagram (with 4 coe‰cients).

Figure 12.9

RTL representation of a FIR filter.

The circuit of figure 12.9 can be constructed in several ways. However, if it is intended for future reuse or sharing, than it should be as generic as possible. In the code presented below, two GENERIC parameters are specified (line 7): n defines the number of filter coe‰cients, while m specifies the number of bits used to represent the input and coe‰cients. For the output, 2 m bits were used. Thus, for example, 16 bits could be used for x, coef, and reg, while 32 bits could be used for all other signals (from the outputs of the multipliers all the way to y).

Notice that the lower section of the filter contains a MAC (multiply-accumulate) pipeline. This circuit is closely related to the MAC circuit discussed in section 12.3. Here too, overflow can happen, so an add/truncate procedure must be included in the design.

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