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Appendix A: Programmable Logic Devices

A1. Introduction

Programmable Logic Devices (PLDs) were introduced in the mid 1970s. The idea was to construct combinational logic circuits that were programmable. However, contrary to microprocessors, which can run a program but posses a fixed hardware, the programmability of PLDs was intended at the hardware level. In other words, a PLD is a general purpose chip whose hardware can be reconfigured to meat particular specifications.

The first PLDs were called PAL (Programmable Array Logic) or PLA (Programmable Logic Array), depending on the programming scheme (discussed later). They used only logic gates (no flip-flops), thus allowing only the implementation of combinational circuits. To circumvent this problem, registered PLDs were launched soon after, which included one flip-flop at each output of the circuit. With them, simple sequential functions could then be implemented as well.

In the beginning of the 1980s, additional logic circuitry was added to each PLD output. The new output cell, called Macrocell, contained (besides the flip-flop) logic gates and multiplexers. Moreover, the cell itself was programmable, allowing several modes of operation. Additionally, it provided a ‘return’ (feedback) signal from the output of the circuit to the programmable array, which gave the PLD greater flexibility. This new PLD structure was called generic PAL (GAL). A similar architecture was known as PALCE (PAL CMOS Electrically erasable/programmable) device.

All these chips (PAL, PLA, registered PLD, and GAL/PALCE) are now collectively referred to as SPLDs (Simple PLDs). The GAL/PALCE device is the only still manufactured in a standalone package.

Later, several GAL devices were fabricated on the same chip, using a more sophisticated routing scheme, more advanced silicon technology, and several additional features (like JTAG support and interface to several logic standards). This approach became known as CPLD (Complex PLD). CPLDs are currently very popular due to their high density, high performance, and low cost (CPLDs under a dollar can be found).

Finally, in the mid 1980s, FPGAs (Field Programmable Gate Arrays) were introduced. FPGAs di¤er from CPLDs in architecture, technology, built-in features, and cost. They are aimed mainly at the implementation of large size, high-performance circuits.

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A summary of the evolution of PLDs is presented in the table below.

A final remark: all PLDs (simple or complex) are non-volatile. They can be OTP (one-time programmable), in which case fuses or antifuses are used, or can be reprogrammable, with EEPROM or Flash memory (Flash is the technology of choice in most new devices). FPGAs, on the other hand, are mostly volatile, for they make use of SRAM to store the connections, in which case a configuration ROM is necessary to load the interconnects at power up. There are, however, non-volatile options, like the use of antifuse. Examples of each alternative will be shown later.

A2. SPLDs (Simple PLDs)

As mentioned above, PAL, PLA, and GAL devices are collectively called Simple PLDs (SPLDs). A description of each of these architectures follows.

PAL Devices

PAL (Programmable Array Logic) chips were introduced by Monolithic Memories in the mid 1970s. Its basic architecture is illustrated symbolically in figure A1, where the little circles represent programmable connections. As can be seen, the circuit is composed of a programmable array of AND gates, followed by a fixed array of OR gates.

The implementation of figure A1 was based on the fact that any combinational function can be represented by a Sum-of-Products (SOP); that is, if a1, a2, . . . , aN are the logic inputs, then any combinational output x can be computed as

x ¼ m1 þ m2 þ þ mM ;

where mi ¼ fi (a1, a2, . . . , aN ) are the minterms of the function x. For example

x ¼ a1a2 þ a2a3a4 þ a1a2a3a4a5:

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inputs

outputs

programmable interconnects

Figure A1

Illustration of PAL architecture.

Hence, the products (minterms) can be obtained by means of AND gates, whose outputs are then connected to an OR gate to compute their sum, thus implementing the SOP equation described above.

The main limitation of this approach was the fact that it allowed only the implementation of combinational functions. To circumvent this problem, registered PALs were launched toward the end of the 1970s. These included a flip-flop at each output (after the OR gates in figure A1), thus allowing the implementation of sequential functions as well (though only very simple ones).

An example of a then popular PAL chip is the PAL16L8 device, which contained 16 inputs and 8 outputs (though only 18 I/O pins were indeed available, because it was a 20-pin DIP package; there were ten IN pins, two OUT pins, and six IN/OUT

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inputs

programmable programmable interconnects interconnects

outputs

Figure A2

Illustration of PLA architecture.

pins (bidirectional), plus VCC and GND). Its registered counterpart was the 16R8 chip (where R stands for Registered).

The early technology employed in the fabrication of PAL devices was bipolar, with 5 V supply and current consumption (with open outputs) around 200 mA. The maximum frequency was of the order of 100 MHz, and the programmable cells were of PROM (fuse links) or EPROM (20min UV erase time) type.

PLA Devices

PLA (Programmable Logic Array) chips were also introduced in the mid 1970s (by Signetics). The basic architecture of a PLA is illustrated symbolically in figure A2. Comparing it with figure A1, we observe that the only fundamental di¤erence between them is that while a PAL has programmable AND connections and fixed OR

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connections, both are programmable in a PLA. The obvious advantage was greater flexibility. However, higher time constants at the internal nodes lowered the circuit speed.

An example of a then popular PLA chip is the Signetics PLS161 device. It contained 12 inputs and 8 outputs, being the AND inputs and the OR inputs all programmable. A total of 48 12-input AND gates were available, followed by a total of 8 48-input OR gates. At the outputs, additional programmable XOR gates were also available.

The technology then employed in the fabrication of PLAs was the same as that of PALs. Though PLAs are also obsolete now, they reappeared recently as a building block in the first family of low power CPLDs, the CoolRunner family (from Xilinx—to be described later).

GAL Devices

The GAL (Generic PAL) architecture was introduced by Lattice in the beginning of the 1980s. It contained several important improvements over the first PAL devices: first, a more sophisticated output cell (Macrocell) was constructed, which included, besides the flip-flop, several gates and multiplexers; second, the Macrocell itself was programmable, allowing several modes of operation; third, a ‘return’ signal from the output of the Macrocell to the programmable array was also included, conferring the circuit more versatility; fourth, EEPROM was employed instead of PROM or EPROM. An electronic signature for identification was also included.

As mentioned earlier, GAL is the only SPLD (Simple PLD) still manufactured in a standalone package. Additionally, it also serves as the basic building block in the construction of most CPLDs (there are exceptions, however, like the CoolRunner CPLD mentioned above, which employs PLAs instead).

Figure A3 shows an example of GAL device, the GAL16V8 (where V stands for Versatile). It is a 16-input, 8-output circuit in a 20-pin package. As can be seen, the actual configuration is eight IN pins (pis 2–9) and eight IN/OUT pins (pins 12–19), plus CLK (pin 1), /OE (–Output Enable, pin 11), VDD (pin 20), and GND (pin 10). At each output there is a Macrocell (after the OR gate), which contains, besides the flip-flop, logic gates and multiplexers. A feedback signal from the Macrocell to the programmable array can also be observed. The programmable interconnections are represented by small circles. Notice that this architecture directly resembles that of a PAL (figure A1), except for the presence of a macrocell at each output and the feedback signal.

Current GAL devices use CMOS technology, 3.3 V supply, EEPROM or Flash technology, and maximum frequency around 250 MHz. Several companies manufacture them (Lattice, Atmel, TI, etc.).

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Figure A3

GAL 16V8 chip.

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Figure A4

CPLD architecture.

A3. CPLD (Complex PLD)

The basic approach in the construction of a CPLD is illustrated in figure A4. As shown, it consists of several PLDs (in general of GAL type) fabricated on a single chip, with a programmable switch matrix used to connect them together and to the I/O pins. Moreover, CPLDs normally contain a few additional features, like JTAG support and interface to other logic standards (1.8 V, 2.5 V, 5 V, etc.).

Regarding figure A4, as an example we can mention the Xilinx XC9500 CPLD. It consists of n PLDs, each resembling a 36V18 GAL device (therefore similar to the 16V8 architecture of figure A3, but with 36 inputs and 18 outputs, instead of 16 inputs and 8 outputs, thus with 18 Macrocells each), where n ¼ 2, 4, 6, 8, 12, or 16.

Several companies manufacture CPLDs, like Altera, Xilinx, Lattice, Atmel, Cypress, etc. Examples from two companies (Altera and Xilinx) are illustrated in tables A1 and A2. As can be seen, over 500 macrocells and over 10,000 gates can be found in these devices.

A4. FPGA

Field Programmable Gate Array (FPGA) devices were introduced by Xilinx in the mid 1980s. They di¤er from CPLDs in architecture, storage technology, number of built-in features, and cost, and are aimed at the implementation of high performance, large-size circuits.

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Table A1

Altera CPLDs.

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Figure A5

FPGA architecture.

The basic architecture of an FPGA is illustrated in figure A5. It consists of a matrix of CLBs (Configurable Logic Blocks), interconnected by an array of switch matrices.

The internal architecture of a CLB (figure A5) is di¤erent from that of a PLD (figure A4). First, instead of implementing SOP expressions with AND gates followed by OR gates (like in SPLDs), its operation is normally based on a LUT (lookup table). Moreover, in an FPGA the number of flip-flops is much more abundant than in a CPLD, thus allowing the construction of more sophisticated sequential circuits. Besides JTAG support and interface to diverse logic levels, other additional features are also included in FPGA chips, like SRAM memory, clock multiplication (PLL or DLL), PCI interface, etc. Some chips also include dedicated blocks, like multipliers, DSPs, and microprocessors.

Another fundamental di¤erence between an FPGA and a CPLD refers to the storage of the interconnects. While CPLDs are non-volatile (that is, they make use of antifuse, EEPROM, Flash, etc.), most FPGAs use SRAM, and are therefore volatile. This approach saves space and lowers the cost of the chip because FPGAs present a very large number of programmable interconnections, but requires an external ROM. There are, however, non-volatile FPGAs (with antifuse), which might be advantageous when reprogramming is not necessary.

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