Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

otherwise, the output bit selected by sel should be low, as illustrated in the truth table of figure 4.1.

The ARCHITECTURE below is totally generic, for the only changes needed to operate with di¤erent values of m and n are in the ENTITY (through sel, line 7, and x, line 8, respectively). In this example, we have used m ¼ 3 and n ¼ 8. However, though this works fine, the use of GENERIC would have made it clearer that m and n are indeed generic parameters. That is indeed the procedure that we will adopt in the other examples that follow (please refer to problem 4.4).

Notice in the code below the use of the following operators: ‘‘þ’’ (line 22), ‘‘*’’ (lines 22 and 24), ‘‘:¼’’ (lines 17, 18, 22, 24, and 27), ‘‘<¼’’ (line 29), and ‘‘¼>’’ (line 17). Notice also the use of the following attributes: HIGH (lines 14–15) and RANGE (line 20).

1 ---------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------------

5ENTITY decoder IS

6PORT ( ena : IN STD_LOGIC;

7sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);

12BEGIN

13PROCESS (ena, sel)

14VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);

15VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;

16BEGIN

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Figure 4.2

Simulation results of example 4.1.

17temp1 := (OTHERS => '1');

18temp2 := 0;

19IF (ena='1') THEN

20FOR i IN sel'RANGE LOOP -- sel range is 2 downto 0

21IF (sel(i)='1') THEN -- Bin-to-Integer conversion

25END IF;

26END LOOP;

27temp1(temp2):='0';

28END IF;

29x <= temp1;

30END PROCESS;

31END generic_decoder;

32---------------------------------------------

The functionality of the encoder above can be verified in the simulation results of figure 4.2. As can be seen, all outputs are high, that is, x ¼ ‘‘11111111’’ (decimal 255), when ena ¼ ‘0’. After ena has been asserted, only one output bit (that selected by sel) is turned low. For example, when sel ¼ ‘‘000’’ (decimal 0), x ¼ ‘‘11111110’’ (decimal 254); when sel ¼ ‘‘001’’ (decimal 1), x ¼ ‘‘11111101’’ (decimal 253); when sel ¼ ‘‘010’’ (decimal 2), x ¼ ‘‘11111011’’ (decimal 251); and so on.

Example 4.2: Generic Parity Detector

Figure 4.3 shows the top-level diagram of a parity detector. The circuit must provide output ¼ ‘0’ when the number of ‘1’s in the input vector is even, or output ¼ ‘1’ otherwise. Notice in the VHDL code below that the ENTITY contains a GENERIC statement (line 3), which defines n as 7. This code would work for any other vector

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Figure 4.3

Generic parity detector of example 4.2.

Figure 4.4

Simulation results of example 4.2.

size, being only necessary to change the value of n in that line. You are invited to highlight the operators and attributes that appear in this design.

1 --------------------------------------------

2ENTITY parity_det IS

3GENERIC (n : INTEGER := 7);

4PORT ( input: IN BIT_VECTOR (n DOWNTO 0);

9BEGIN

10PROCESS (input)

11VARIABLE temp: BIT;

12BEGIN

13temp := '0';

14FOR i IN input'RANGE LOOP

15temp := temp XOR input(i);

16END LOOP;

17output <= temp;

18END PROCESS;

19END parity;

20 --------------------------------------------

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Figure 4.5

Generic parity generator of example 4.3.

Simulation results from the circuit synthesized with the code above are shown in figure 4.4. Notice that when input ¼ ‘‘00000000’’ (decimal 0), the output is ‘0’, because the number of ‘1’s is even; when input ¼ ‘‘00000001’’ (decimal 1), the output is ‘1’, because the number of ‘1’s is odd; and so on.

Example 4.3: Generic Parity Generator

The circuit of figure 4.5 must add one bit to the input vector (on its left). Such bit must be a ‘0’ if the number of ‘1’s in the input vector is even, or a ‘1’ if it is odd, such that the resulting vector will always contain an even number of ‘1’s (even parity).

A VHDL code for the parity generator is shown below. Once again, you are invited to highlight the operators and attributes used in the design.

1 -----------------------------------------------

2ENTITY parity_gen IS

3GENERIC (n : INTEGER := 7);

4PORT ( input: IN BIT_VECTOR (n-1 DOWNTO 0);

6END parity_gen;

7 -----------------------------------------------

8 ARCHITECTURE parity OF parity_gen IS

9BEGIN

10PROCESS (input)

11VARIABLE temp1: BIT;

12VARIABLE temp2: BIT_VECTOR (output'RANGE);

13BEGIN

14temp1 := '0';

15FOR i IN input'RANGE LOOP

16temp1 := temp1 XOR input(i);

17temp2(i) := input(i);

18END LOOP;

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Figure 4.6

Simulation results of example 4.3.

Table 4.1

Operators.

19temp2(output'HIGH) := temp1;

20output <= temp2;

21END PROCESS;

22END parity;

23-----------------------------------------------

Simulation results are presented in figure 4.6. As can be seen, when input ¼ ‘‘0000000’’ (decimal 0, with seven bits), output ¼ ‘‘00000000’’ (decimal 0, with eight bits); when input ¼ ‘‘0000001’’ (decimal 1, with seven bits), output ¼ ‘‘10000001’’ (decimal 129, with eight bits); and so on.

4.7 Summary

A summary of VHDL operators and attributes is presented in tables 4.1 and 4.2, respectively. The constructs that are not synthesizable (or have little synthesis support) are marked with the ‘‘)’’ symbol.

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Table 4.2

Attributes.

4.8Problems

Problems 4.1 to 4.3 are based on the following signal declarations:

Problem 4.1: Operators (fill in the blanks)

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Problem 4.2: Attributes (fill in the blanks)

Problem 4.3: Legal and Illegal Operations

Verify whether each of the operations below is legal or illegal. Briefly justify your answers.

b(0) AND a a + d(7)

NOT b XNOR c c + d

e - f

IF (b<c) ...

IF (b>=a) ...

IF (f/=e) ...

IF (e>d) ...

b sra 1 c srl -2 f ror 3 e*3

5**5

f/4

e/3

d <= c

d(6 DOWNTO 3) := b e <= d

f := 100

Problem 4.4: Generic Decoder

The questions below are related to decoder circuit designed in example 4.1.

(a) In order for that design to operate with another vector size, two values must be changed: the range of sel (line 7) and the range of x (line 8). We want now to trans-

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form that design in a truly generic one. In order to do so, introduce a GENERIC statement in the ENTITY, specifying the number of bits of sel (say, n ¼ 3), then replace the upper range limits of sel and x by an attribute which is a function of n. Synthesize and simulate your circuit in order to verify its functionality.

(b) In example 4.1, a binary-to-integer conversion was implemented (lines 20–26). This conversion could be avoided if sel had been declared as an INTEGER. Modify the code, declaring sel as an INTEGER. The code should remain truly generic, so the range of sel must be specified in terms of n. Synthesize and simulate your new code.

Problem 4.5

List all operators, attributes and generics employed in examples 4.2 and 4.3.

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