Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

3.8Data Conversion

VHDL does not allow direct operations (arithmetic, logical, etc.) between data of di¤erent types. Therefore, it is often necessary to convert data from one type to another. This can be done in basically two ways: or we write a piece of VHDL code for that, or we invoke a FUNCTION from a pre-defined PACKAGE which is capable of doing it for us.

If the data are closely related (that is, both operands have the same base type, despite being declared as belonging to two di¤erent type classes), then the std_logic_1164 of the ieee library provides straightforward conversion functions. An example is shown below.

Example: Legal and illegal operations with subsets.

Several data conversion functions can be found in the std_logic_arith package of the ieee library. They are:

conv_integer(p) : Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an INTEGER value. Notice that STD_LOGIC_ VECTOR is not included.

conv_unsigned(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an UNSIGNED value with size b bits.

conv_signed(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to a SIGNED value with size b bits.

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conv_std_logic_vector(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_LOGIC to a STD_LOGIC_VECTOR value with size b bits.

Example: Data conversion.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

...

SIGNAL a: IN UNSIGNED (7 DOWNTO 0);

SIGNAL b: IN UNSIGNED (7 DOWNTO 0);

SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

...

y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);

--Legal operation: a+b is converted from UNSIGNED to an

--8-bit STD_LOGIC_VECTOR value, then assigned to y.

Another alternative was already mentioned in the previous section. It consists of using the std_logic_signed or the std_logic_unsigned package from the ieee library. Such packages allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED, respectively.

Besides the data conversion functions described above, several others are often o¤ered by synthesis tool vendors.

3.9 Summary

The fundamental synthesizable VHDL data types are summarized in table 3.2.

3.10 Additional Examples

We close this chapter with the presentation of additional examples illustrating the specification and use of data types. The development of actual designs from scratch will only be possible after we conclude laying out the basic foundations of VHDL (chapters 1 to 4).

Example 3.1: Dealing with Data Types

The legal and illegal assignments presented next are based on the following type definitions and signal declarations:

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Table 3.2

Synthesizable data types.

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x <= "11111110";

y <= ('1','1','1','1','1','1','0','Z'); z <= "11111" & "000";

x <= (OTHERS => '1');

y <= (7 =>'0', 1 =>'0', OTHERS => '1');

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z(j) <= '0'; w1(i,j) <= '0'; w2(i)(j) <= '0'; w3(i)(j) <= '0';

END LOOP;

END LOOP;

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Example 3.2: Single Bit Versus Bit Vector

This example illustrates the di¤erence between a single bit assignment and a bit vector assignment (that is, BIT versus BIT_VECTOR, STD_LOGIC versus STD_ LOGIC_VECTOR, or STD_ULOGIC versus STD_ULOGIC_VECTOR).

Two VHDL codes are presented below. Both perform the AND operation between the input signals and assign the result to the output signal. The only di¤erence between them is the number of bits in the input and output ports (one bit in the first, four bits in the second). The circuits inferred from these codes are shown in figure 3.2.

Example 3.3: Adder

Figure 3.3 shows the top-level diagram of a 4-bit adder. The circuit has two inputs (a, b) and one output (sum). Two solutions are presented. In the first, all signals are of type SIGNED, while in the second the output is of type INTEGER. Notice in solution 2 that a conversion function was used in line 13, for the type of a þ b does not match that of sum. Notice also the inclusion of the std_logic_arith package (line 4 of each solution), which specifies the SIGNED data type. Recall that a SIGNED value is represented like a vector; that is, similar to STD_LOGIC_VECTOR, not like an INTEGER.

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1 ----- Solution 1: in/out=SIGNED ----------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE ieee.std_logic_arith.all;

5 ------------------------------------------

6ENTITY adder1 IS

7PORT ( a, b : IN SIGNED (3 DOWNTO 0);

12BEGIN

13sum <= a + b;

14END adder1;

15 ------------------------------------------

x(1)

b(1)

a(2)

x(2)

b(2)

a(3)

x(3)

b(3)

Figure 3.2

Circuits inferred from the codes of example 3.2.

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Figure 3.4

Simulation results of example 3.3.

1 ------ Solution 2: out=INTEGER -----------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 USE ieee.std_logic_arith.all;

5 ------------------------------------------

6ENTITY adder2 IS

7PORT ( a, b : IN SIGNED (3 DOWNTO 0);

12BEGIN

13sum <= CONV_INTEGER(a + b);

14END adder2;

15 ------------------------------------------

Simulation results (for either solution) are presented in figure 3.4. Notice that the numbers are represented in hexadecimal 2’s complement form. Since the input range is from 8 to 7, its representation is 7 ! 7, 6 ! 6, . . . , 0 ! 0, 1 ! 15, 2 ! 14,

. . . , 8 ! 8. Likewise, the output range is from 16 to 15, so its representation is 15 ! 15, . . . , 0 ! 0, 1 ! 31, . . . , 16 ! 16. Therefore, 2H þ 4H ¼ 06H (that is, 2 þ 4 ¼ 6), 4H þ 8H ¼ 1CH (that is, 4 þ ( 8) ¼ 4), etc., where H ¼ Hexadecimal.

3.11Problems

The problems below are based on the following TYPE definitions and SIGNAL declarations:

TYPE array1 IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;

TYPE array2 IS ARRAY (3 DOWNTO 0, 7 DOWNTO 0) OF STD_LOGIC; TYPE array3 IS ARRAY (3 DOWNTO 0) OF array1;

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SIGNAL a : BIT;

SIGNAL b : STD_LOGIC;:

SIGNAL x : array1;

SIGNAL y : array2;

SIGNAL w : array3;

SIGNAL z : STD_LOGIC_VECTOR (7 DOWNTO 0);

Problem 3.1

Determine the dimensionality (scalar, 1D, 2D, or 1Dx1D) of the signals given. Also, write down a numeric example for each signal.

Problem 3.2

Determine which among the assignments in table P3.2 are legal and which are illegal. Briefly justify your answers. Also, determine the dimensionality of each assignment (on both sides).

Problem 3.3: Subtypes

Consider the pre-defined data types INTEGER and STD_LOGIC_VECTOR. Consider also the user-defined types ARRAY1 and ARRAY2 specified above. For each, write down a possible SUBTYPE.

Problem 3.4: ROM

Consider the implementation of a ROM (read-only memory). It can be done utilizing a 1Dx1D CONSTANT. Say that the ROM must be organized as a pile of eight words of four bits each. Create an array called rom, then define a signal of type rom capable of solving this problem. Choose the values to be stored in the ROM and declare them along with your CONSTANT, that is, ‘‘CONSTANT my_rom: rom :=(values);’’.

Problem 3.5: Simple Adder

Rewrite solution 1 of example 3.3, but this time with all input and output signals of type STD_LOGIC_VECTOR. (Suggestion: review section 3.8).

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