Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

FIGURE 6.23

BCD Adder (11⁄2 Digit Output)

4-bit Adder

Figure 6.23 shows how we can add two BCD digits and get a corrected output. The BCD adder circuit consists of a standard 4-bit parallel adder to get the binary sum and a code converter to translate it into BCD.

The Binary-to-BCD code converter operates on the binary inputs as follows:

1.A carry output is generated if the binary sum is in the range 01010 sum 10011 (BCD equivalent: 1 0000 sum 1 1001).

2.If the binary sum is less than 01001, the output is the same as the input.

3.If the sum is in the range 01010 sum 10011, the four LSBs of the input must be corrected to a BCD value. This can be done by adding 0110 to the four LSBs of the in-

put and discarding any resulting carry. We add 01102 (610) because we must account for six unused codes.

Let’s look at how each of these requirements can be implemented by a digital circuit.

Carry Output

The carry output will be automatically 0 for any uncorrected sum from 00000 to 01001 and automatically 1 for any sum from 10000 to 10011. Thus, if the binary adder’s carry output, which we will call C4 , is 1, the BCD adder’s carry output, C4, will also be 1.

Any sum falling between these ranges, that is, between 01010 and 01111, must have its MSB modified. This modifying condition is a function, designated C4 , of the binary adder’s sum outputs when its carry output is 0. This function can be simplified by a Karnaugh map, as shown in Figure 6.24, resulting in the following Boolean expression.

C4 4 3 4 2

The BCD carry output C4 is given by:

C4 C4 C4

C4 4 3 4 2

The BCD carry circuit is shown in Figure 6.25.

Sum Correction

The four LSBs of the binary adder output need to be corrected if the sum is 01010 or greater and need not be corrected if the binary sum is 01001 or less. This condition is indicated by the BCD carry. Let us designate the binary sum outputs as 4 3 2 1 and the BCD sum outputs as 4 3 2 1.

If C4 0, 4 3 2 1 4 3 2 1 0000;

If C4 1, 4 3 2 1 4 3 2 1 0110.

Figure 6.26 shows a BCD adder, complete with a binary adder, BCD carry, and sum correction. A second parallel adder is used for sum correction. The B inputs are the uncorrected binary sum inputs. The A inputs are either 0000 or 0110, depending on the value of the BCD carry.

FIGURE 6.26

BCD Adder

6.8 • Carry Generation in MAX PLUS II 263

Multiple-Digit BCD Adders

Several BCD adders can be cascaded to add multidigit BCD numbers. Figure 6.27 shows a 412 -digit BCD adder. The carry output of the most significant digit is considered to be a half-digit since it can only be 0 or 1. The output range of the 412 -digit BCD adder is 00000 to 19999.

FIGURE 6.27

41⁄2-Digit BCD Adder

BCD adders are cascaded by connecting the code converter carry output of one stage to the binary adder carry input of the next most significant stage. Each BCD output digit represents a decade, designated as the units, tens, hundreds, thousands, and ten thousands digits.

SECTION 6.7 REVIEW PROBLEM

6.11What is the maximum BCD sum of two 3-digit numbers with no carry input? How many digits are required to display this result on a numerical output?

6.8Carry Generation in MAX PLUS II

K E Y T E R M S

Speed grade A specification that indicates the internal delay time that can be expected of a CPLD.

Expander buffer A MAX PLUS II primitive that supplies an inverted product term for general use within a CPLD.

The VHDL adder circuits implemented in Section 6.6 were all defined using a ripple carry format. Is it necessary to design a fast carry circuit when compiling one of these adder designs in MAX PLUS II? Probably not.

Recall that the design strategy behind the fast carry circuit was to flatten the gate network, that is, to replace a long network (many gates for the carry bit to pass through) with a wide one (fewer levels of gating). Also recall that any combinational logic function can be implemented as a sum-of-products (SOP) network, which inherently is a very flat network form.

The internal circuit of a MAX7000S CPLD is a programmable SOP network. In order to program such a device, the MAX PLUS II compiler must analyze the design entity, break it into product terms and reassemble it as an SOP network. (This is an oversimplification. Sometimes SOP outputs are fed back into the circuit to be reused by other parts of the circuit, thus lengthening the logic path.)

MAX PLUS II allows us to choose a style of logic synthesis that balances circuit speed and chip area occupied by the programmed circuit. The styles can be user-defined or we can use one of three predefined synthesis styles called Normal, Fast, and WYSIWYG (What You See Is What You Get). Each one of these styles is optimized for speed, area, or a compromise. The Normal and Fast styles disassemble the design entity and reassemble it after optimizing the logic according to the style rules. The WYSIWYG style allows us (rather than the compiler) to largely define the logic synthesis without altering our design format by very much.

To choose a synthesis style, select Global Project Logic Synthesis, from the MAX PLUS II Assign menu, as shown in Figure 6.28. A drop-down menu in the resulting dialog box, shown in Figure 6.29, allows us to select one of the three Altera-defined synthesis styles.

N O T E

To use the WYSIWYG style, you must also check the box that says Multi-Level

Synthesis for MAX 5000/7000 Devices.

We can calculate the circuit delays for an adder by running the compiled design through the MAX PLUS II Timing Analyzer. Figure 6.30 shows an example of such an analysis for the parallel adder add4par.vhd with a Normal synthesis style and an EPM7128SLC84-7 as the selected device.

6.8 • Carry Generation in MAX PLUS II 265

FIGURE 6.30

Delay matrix for a 4-bit adder (Normal Synthesis)

The values in the Destination columns are the delays from logic level changes on the inputs specified by the Source rows. For example, a change on input a1 reaches the output sum1 in 7.5 ns and sum4 in 12.5 ns. Most of the entries in the c4 column have two values (7.5 ns and 11.5 ns), indicating that the delay to output carry is the same from all input bits (i.e., a fast carry). The actual delay to c4 will depend on the logic level change that takes place on the source line and thus which logic path is taken. The delay time of 7.5 ns is about the lowest value possible in the EPM7128SLC84-7 device. (The “ 7” tells us that the chip has a speed grade of minus 7, meaning an internal delay of about 7 ns.)

Figure 6.31 shows the timing analysis of the same adder with a WYSIWYG synthesis style. (The synthesis style is the only design change.) In this analysis, the delay from an input bit to c4 varies from 7.5 ns (from a4 or b4) to as much as 16.5 ns (for a1, b1, a2, or b2). Since the lower-order bits result in a longer delay to the carry bit, we can infer that the compiler has not synthesized a fast carry circuit.

FIGURE 6.31

Delay matrix for a 4-bit adder (WYSIWYG Synthesis)

We can examine the actual equations from the MAX PLUS II report file to confirm our assessment. The synthesized equations for c4 are given below.

WYSIWYG Synthesis:

——Node name is ´c4´ ´|full_add:adder4| :12´

——Equation name is ´c4´, type is output

c4 LCELL( _EQ001 $ GND); _EQ001 a3 & b3 & b4

#b4 & _LC113 & _LC114

#a3 & a4 & b3

#a4 & _LC113 & _LC114

#a4 & b4;

——Node name is ´|full_add:adder2|:12´

——Equation name is ´_LC113´, type is buried

——Node name is ´|full_add:adder3|:9´

——Equation name is ´_LC114´, type is buried _LC114 LCELL( b3 $ a3);

Normal synthesis:

——Node name is ´c4´

——Equation name is ´c4´, location is LC123, type is output. c4 LCELL ( EQ001 $ VCC);

#!a3 & !b3 & _X004

#!a4 & !b4;

_X001 EXP ( a2 & b2); _X002 EXP ( b1 & c0); _X003 EXP ( a3 & b3); _X004 EXP ( a4 & b4);

The function EXP(signal) is for a MAX PLUS II primitive called an expander buffer, which represents a shared logic expander in the CPLD. There will be more detail about this type of buffer in Chapter 8, but for now, just be aware that this type of buffer supplies inverted product terms for general use within the CPLD.

The Normal synthesis mode generates a sum-of-products equation that uses a number of expanders, but only one logic cell (i.e., one SOP output), indicated as LC123. The WYSIWYG synthesis uses an unnumbered output logic cell, which in turn uses two other logic cell outputs (LC113 and LC114) as inputs. Thus, in the Normal synthesis mode, the input signals propagate through one logic cell, and in the WYSIWYG mode, the input signals go through two layers of logic cells, increasing the path length, and thus the delay.

What can we conclude? If MAX PLUS II is allowed to synthesize a design for a full adder in the defined Normal style, it will optimize the design equations to produce as flat a network as possible. Thus we do not need to explicitly design an adder circuit to have a fast carry function.