C H A P T E R 1 0 •
2digit.gdf count_8.vhd sev_segv.vhd
State Machine Design
If the debouncer is working properly, the seven-segment display should advance by one each time pb_in is pressed. If the debouncer is not working, the display will change by
with each switch press.
files for the debouncer and test circuit components are supplied this book in the folder drive:\Student Files\Chapter 10\. To use these files, create a symbol for each one (File menu; Project; Set Project to Current File;
then File menu; Create Default Symbol) and draw the Graphic Design File of Figure 10.26. Alternatively, you can instantiate each file as a component in a VHDL design entity
(all components are designed in VHDL) and connect them together with internal signals.
Behaviorally Designed Switch Debouncer
We can also design a switch debouncer by using a behavioral state machine description in VHDL. In order to do so, we need to define the operation of the circuit with a state diagram, as in Figure 10.27.
FIGURE 10.27 |
pb-in, pb-out/pb-out |
State Diagram for a Behaviorally |
01/1 |
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Designed Switch Debouncer |
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10/0 |
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s0 |
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00 |
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00/0 |
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11/1 |
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01/1 |
s1 |
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01 |
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10/0 |
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00/0 |
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01/1 |
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11/1 |
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s2 |
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10/0 |
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02 |
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00/1 |
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00/0 |
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11/0 |
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11/1 |
01/1 |
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s3 |
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10/0 |
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03 |
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Transitions between states are determined by comparing pb_in and pb_out. If they are the same (00 or 11), the machine advances to the next state; if they are different (01 or 10), the machine reverts to the initial state, s0. At any point in the state diagram (including state s3, the last state), the machine will reset if pb_in and pb_out are different, indicating a bounce on the input.
If pb_in and pb_out are the same for four clock pulses, the input is deemed to be stable. Only at this point will the output change to its opposite state.
N O T E
In the shift register–based debouncer, the circuit advanced to the next state if the shift register input and output were different and reset if they were the same. This might appear to be opposite to our behavioral description, but it is not if you look carefully. The shift register debouncer circuit inverts pb_in before applying the signal to the serial input of the shift register. Therefore, viewed from the circuit input and output terminals, rather than at the shift register input and output, the description is the same in both cases.
10.4 • Switch Debouncer for a Normally Open Pushbutton Switch |
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The VHDL code corresponding to the behavioral description of the switch debouncer is given next. The only output change is specified on the transition from state s3 to s0 when pb_in pb_out. Since no change is allowed at any other time, no other output state needs to be specified.
--dbc_behv.vhd
--Behavioral definition of a switch debouncer LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY dbc_behv IS
PORT(
clk, pb_in : IN STD_LOGIC; pb_out : BUFFER STD_LOGIC);
END dbc_behv;
ARCHITECTURE debounce of dbc_behv IS
TYPE sequence IS (s0, s1, s2, s3);
SIGNAL state: sequence;
dbc_behv.vhd dbc_behv.scf
IF (clk‘EVENT and clk=‘1’) THEN
CASE state IS
WHEN s0=> IF (pb_in = pb_out) THEN state <= s1;
ELSE
state <= s0; END IF;
WHEN s1=> IF (pb_in = pb_out) THEN state <= s2;
ELSE
state <= s0; END IF;
WHEN S2=> IF (pb_in = pb_out) THEN state <= s3;
ELSE
state <= s0; END IF;
WHEN s3=> IF (pb_in = pb_out) THEN state <= s0;
pb_out <= not pb_out;
ELSE
state <= s0; END IF;
WHEN others => state <= s0;
END CASE;
END IF;
END PROCESS;
END debounce;
Figure 10.28 shows a simulation of the behaviorally-designed switch debouncer. State s1 through s3 are of too short a duration to show properly on the simulation, so further details of the simulation are shown in Figures 10.29 and 10.30.
482 C H A P T E R 1 0 • State Machine Design
FIGURE 10.28
Simulation of a Behaviorally Designed Switch Debouncer
FIGURE 10.29
Simulation Detail (Behaviorally Designed Switch Debouncer)
FIGURE 10.30
Simulation Detail (Behaviorally Designed Switch Debouncer)
Note that the behaviorally designed switch debouncer does not have a built-in clock divider. If we were to use the circuit on the Altera UP-1 board, we would need to include a divide-by-216 counter to the circuit, as shown in Figure 10.31.
SECTION 10.4 REVIEW PROBLEM
10.4What is the fastest acceptable clock rate for the shift register portion of the debouncer in Figure 10.24 if the pushbutton switch bounces for 15ms?
484 C H A P T E R 1 0 • State Machine Design
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0/00 |
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start |
in1/out1, out2 |
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X /01 |
000 |
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1/00 |
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pulse2 |
wait1 |
1/00 |
100 |
001 |
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X /10 |
0/00 |
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pulse1 |
wait2 |
011 |
010 |
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1/00 |
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0/00 |
FIGURE 10.32
State Diagram for a Two-pulse Generator
10.5 Unused States in State Machines
In our study of counter circuits in Chapter 9, we found that when a counter modulus is not equal to a power of two there were unused states in the counter’s sequence. For example, a mod-10 counter has six unused states, as the counter requires four bits to express ten states and the maximum number of 4-bit states is sixteen. The unused states (1010, 1011, 1100, 1101, 1110, and 1111) have to be accounted for in the design of a mod-10 counter.
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The same is true of state machines whose number of states does not equal a power of |
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two. For instance, a machine with five states requires three state variables. There are up to |
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eight states available in a machine with three state variables, leaving three unused states. |
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Figure 10.32 shows the state diagram of such a machine. |
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Unused states can be dealt with in two ways: they can be treated as don’t care states, |
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or they can be assigned specific destinations in the state diagram. In the latter case, the |
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safest destination is the first state, in this case the state called start. |
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EXAMPLE 10.4 |
Redraw the state diagram of Figure 10.32 to include the unused states of the machine’s |
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state variables. Set the unused states to have a destination state of start. Briefly describe |
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the intended operation of the state machine. |
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Solution Figure 10.33 shows the revised state diagram. |
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The machine begins in state start and waits for a HIGH on in1. The machine then |
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makes a transition to wait1 and stays there until in1 goes LOW again. The machine goes to |
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wait2 and stays there until in1 goes HIGH and then makes an unconditional transition to |
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pulse1 on the next clock pulse. Until this point, there is no change in either output. |
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The machine makes an unconditional transition to pulse2 and makes out1 go HIGH. |
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The next transition, also unconditional, is to start, when out1 goes LOW and out2 goes |
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HIGH. If in1 is LOW, the machine stays in start. Otherwise, the cycle continues as above. |
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In either case, out2 goes LOW again. |