Файл: Embedded Controller Hardware Design (Ken Arnold, 2001).pdf
ВУЗ: Не указан
Категория: Не указан
Дисциплина: Не указана
Добавлен: 13.06.2025
Просмотров: 2645
Скачиваний: 0
17CHAPTER ONE
Review of Electronics Fundamentals
curve, Vo at Io max. As a result, |
max |
V OH |
V OL |
||
the best we can do is to look |
OLmax |
||||
|
OH |
Vcc |
||||
at the output characteristics |
V |
||||
|
I |
|||||
graphically, as shown in |
OH max |
I |
|||
Figure 1-17. |
VOL max |
||||
-I OH |
IOL |
||||
Logic Symbols |
Figure 1-17: Output voltage Vo versus current Io. |
||||
Logic symbols are used to represent the logic functions in a more abstract way, allowing the designer to specify the logical function of a circuit without getting into the details of the underlying components (such as the transistors and resistors). The logic symbols used in this text represent those that are most commonly used in commercial documentation. There are other standards, such as the ANSI/IEEE standard gate level symbols, but they are not encountered as frequently in practice. Figure
1-18 shows the logic symbols for |
A |
F |
A |
F |
A |
F |
A |
F |
|||||||||||||||
B |
B |
B |
|||||||||||||||||||||
OR |
XOR |
||||||||||||||||||||||
different gates, and their functions |
Buffer |
AND |
|||||||||||||||||||||
F = A |
F = AB |
F = A+B |
F = A+B |
||||||||||||||||||||
are described in the truth tables. |
A F |
A B F |
A B F |
A B F |
|||||||||||||||||||
The logic symbols in Figure 1-18 |
0 |
0 |
0 0 |
0 |
0 0 |
0 |
0 0 |
0 |
|||||||||||||||
1 |
1 |
0 1 |
0 |
0 1 |
1 |
0 1 |
1 |
||||||||||||||||
show the shapes and Boolean logic |
1 0 |
0 |
1 0 |
1 |
1 0 |
1 |
|||||||||||||||||
functions for the most common |
1 1 |
1 |
1 1 |
1 |
1 1 |
0 |
|||||||||||||||||
gate configurations. The buffer |
A |
F |
A |
F |
A |
F |
A |
F |
|||||||||||||||
device is a triangle—the symbol |
|||||||||||||||||||||||
B |
B |
B |
|||||||||||||||||||||
Inverter |
NAND |
NOR |
XNOR |
||||||||||||||||||||
for an amplifier—because it |
|||||||||||||||||||||||
F = A |
F = AB |
F = A+B |
F = A+B |
||||||||||||||||||||
amplifies the input signal, allowing |
|||||||||||||||||||||||
A |
F |
A B |
F |
A B |
F |
A B |
F |
||||||||||||||||
an increase in the number of loads |
0 |
1 |
0 0 |
1 |
0 0 |
1 |
0 0 |
1 |
|||||||||||||||
that can be driven. Note that a |
1 |
0 |
0 1 |
1 |
0 1 |
0 |
0 1 |
0 |
|||||||||||||||
1 0 |
1 |
1 0 |
0 |
1 0 |
0 |
||||||||||||||||||
small circle, often referred to as a |
|||||||||||||||||||||||
1 1 |
0 |
1 1 |
0 |
1 1 |
1 |
||||||||||||||||||
“bubble,” on an input or output |
Figure 1-18: Logic symbols, symbolic notation, |
||||||||||||||||||||||
terminal designates a logical inver- |
|||||||||||||||||||||||
and truth tables. |
|||||||||||||||||||||||
sion. Thus the inverter is shown as |
|||||||||||||||||||||||
a triangle (amplifier) with a bubble on the output to signify the logic level |
|||||||||||||||||||||||
inversion on the output. The logic voltage levels for TTL logic are: |
|||||||||||||||||||||||
Positive Logic |
Corresponding TTL Logic Voltages |
||||||||||||||||||||||
0 = false = lowest voltage level |
0 = input voltages 0 to 0.8 volts (low) |
||||||||||||||||||||||
1 = true = highest voltage level |
1 = input voltages 2 to 5 volts (high) |
||||||||||||||||||||||
18EMBEDDED CONTROLLER
Hardware Design
This means that a TTL compatible logic input is guaranteed to respond to an input signal between 0 and 0.8 volts as a logic zero, and input voltages from 2 to 5 volts as a logic one. Note that voltages between 0.8 and 2 volts are not valid logic levels.
Logic voltage levels are different for different types of logic, but the most common logic levels are those corresponding to the original TTL (transistor transistor logic), using a 5 volt power supply. CMOS levels, using 3 or 5 volt power, are also common. TTL and CMOS logic—like almost every other type of logic in common use —are called positive logic because the most positive voltage corresponds to the logic one value.
Tri-State Logic
Tri-state logic does not refer to orderly thinking in a three state geographic region! When we speak of binary (base two number) values, we mean that a given bit or logic signal can take on either one of two valid states (zero or one) at any instant in time. A logic gate that is not forcing its output to be either one or zero is said to be tri-stated. Tri-state logic does not refer to base three numbers, but rather to a third invalid logic state when the output of a logic device is neither sinking nor sourcing current. This so-called third state is really an undefined
condition, because the |
Tri-State Inverting Buffer |
Output ENabled |
Output DISabled |
||||||||||||
? |
|||||||||||||||
device output is not |
A |
Y |
A |
||||||||||||
A |
A |
OFF |
|||||||||||||
forcing a logic level on |
Input |
Output |
HI-Z |
||||||||||||
OE |
1 |
0 |
|||||||||||||
its output. It is said to be |
|||||||||||||||
Truth Table |
|||||||||||||||
in a floating, high impedance, passive, or Hi-Z state, since the output circuits are effectively disconnected. A tri-state driver connected to one signal wire of the bus is shown in Figure 1-19.
A |
OE |
Y |
NC |
|||||||
0 |
1 |
1 |
||||||||
Output |
Output |
|||||||||
1 |
1 |
0 |
||||||||
Switch |
Switch |
|||||||||
0 |
0 |
? |
Hi-Z |
ON |
OFF |
|||||
(closed) |
(open) |
|||||||||
1 |
0 |
? |
Hi-Z |
|||||||
Symbol and Function |
Equivalent Circuit – Active and Passive |
|||||||||
Figure 1-19: Active and passive states of a tri-state buffer.
On the left is an inverting buffer with an enabled tri-state output. On the right side is an example showing two of the same type of buffers, with the top device in the disabled or passive state, and the lower device is enabled
19CHAPTER ONE
Review of Electronics Fundamentals
or actively driving the data bus to a logic one level. The control signal deter mines whether the output is passive or active, and is called the output enable or OE signal. The device shown above is actively driving the bus whenever the OE control line is at a logic one level, and is passive when the OE line is at a logic zero level. Most of the time, output enable signals are active low, mean ing that the output is enabled when the /OE signal is low, and passive when the /OE signal is high. This is shown on the logic symbol with an inversion bubble where the enable signal enters the logic device.
As computer circuits become more dense and complex, the connecting wires have become increasingly difficult to route and interconnect. This is especially true on a densely packed integrated circuit, where it turns out that the wiring is more valuable than the logic gates! On one common CPU chip, 68% of the chip area is used for interconnect wiring. Even on a circuit board, it is impor tant to use the board wiring in an efficient way. Since there are many parallel address and data lines that must go to multiple chips, the multiplexing approach makes it practical to connect many devices. The purpose for using tri-state logic is to allow multiple devices to share wires by taking turns one at a time. This may sound a bit silly, but it is just one form of multiplexing, or sharing a resource that needs to be allocated among multiple devices. When the resource is a collection of parallel data wires, referred to as a data bus, and the bus is shared by multiple microcomputer CPU and peripheral devices transferring information one at a time in sequence, it is referred to as a multiplexed data bus.
Timing Diagrams
The timing diagram is the standard “language” of illustrating timing relation ships between different parts of a design. In order to understand the relation ship of different signals with respect to time, it is necessary to learn how to read and interpret timing diagrams. Figure 1-20 shows examples of asynchro nous (un-clocked or combinatorial gates) and synchronous (clocked flip-flop) logic. The notation used in this book is representative of that used in most component specifications. Timing specifications, such as delay, setup, and hold times, specify the limits under which the device is guaranteed to operate as intended. If those specifications are violated, the device may very well operate correctly most of the time. However, a change in temperature, voltage, or variations from unit to unit may make the circuit unreliable. The most
20EMBEDDED CONTROLLER
Hardware Design
undesirable result of timing violations is that the circuit makes very infre quent errors, perhaps one error in hundreds of hours of operation. If you have ever wondered why your PC crashes mysteriously for no apparent reason, timing specification violations may well be the cause!
NAND |
NOR |
|||
A |
F |
A |
D |
Q |
B |
B |
F |
Q |
|
CK |
||||
A |
CK |
|||
Rise |
Delay |
Hold |
||
B |
Time |
|||
D |
||||
Delay |
Setup |
|||
F=A*B |
Fall |
Q |
||
Time |
||||
G=A+B |
Q |
Figure 1-20: Timing diagram notation examples.
Timing relationships are particularly important for signals that are “time shared” on a single wire. A group of wires that carries different information at different times is also called a bus.
Multiplexed Bus
In order to describe the timing of such a shared data bus, it is neces sary to define some notation for timing diagrams. The notation used in this book is shown in Figure 1-21.
The terminology for timing param eters is covered in a later chapter, but the basic concept for time multiplexed data on a bus is shown in Figure 1-21. The two devices are alternately enabled to drive the data bus wire, allowing each to drive the bus in turn. Only one device is allowed to drive the bus at a time when it is operating correctly.
Tri-State Data Bus To Other Devices
Device A |
Device B |
Bus |
Bus |
||
Data |
Data |
||
to A |
to B |
||
Data |
DA |
DB |
Data |
to Bus |
to Bus |
||
from A |
from B |
||
Enable |
OEA |
OEB |
Enable |
Output |
Output |
||
A to Bus |
BUS |
B to Bus |
|
Data Bus |
|||
OEA |
DA |
Data from A |
New Data from A |
|
OEB |
|||
DB |
Data from B |
||
BUS |
A |
B |
new A |
Figure 1-21: Time multiplexed data bus and timing.