Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

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628

Appendix C

BTFSC

Bit Test f, Skip if Clear

Syntax:

[ label ] BTFSC

f,b

Operands:

f in range 0 to 127

b in range 0 to 7

Operation:

skip next instruction if (f<b>) = 0

Status Affected:

None

Description:

If bit 'b' in register 'f' is '0' then the next

instruction is skipped. If bit 'b' is '0' then the

next instruction (fetched during the current in-

struction execution) is discarded, and a NOP

is executed instead, making this a 2 cycle

instruction.

Words:

1

Example 1:

repeat:

btfsc

reg1,4

goto

repeat

Case 1: Before Instruction

PC = $

reg1 = xxx0 xxxx After Instruction

Since reg1<4>= 0,

PC = $ + 2 (goto skipped)

Case 2: Before Instruction

PC = $

reg1= xxx1 xxxx After Instruction

Since FLAG<4>=1,

PC = $ + 1 (goto executed)

Mid-range Instruction Set

629

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] BTFSC

f,b

Operands:

f in range 0 to 127

b in range 0 to 7

Operation:

skip next instruction if (f<b>) = 1

Status Affected:

None

Description:

If bit 'b' in register 'f' is '1' then the next

instruction is skipped. If bit 'b' is '0' then the

next instruction (fetched during the current

instruction execution) is discarded, and a NOP

is executed instead, making this a 2 cycle

instruction.

Words:

1

Cycles:

1(2)

repeat:

btfss

reg1,4

goto

repeat

Case 1: Before Instruction

PC = $

Reg1 = xxx1 xxxx

After Instruction

Since Reg1<4>= 1,

PC = $ + 2 (goto skipped)

Case 2: Before Instruction

PC = $

Reg1 = xxx0 xxxx

After Instruction

Since Reg1<4>=0,

PC = $ + 1 (goto executed)

630

Appendix C

CALL

Call Subroutine

Syntax:

[ label ] CALL

k

Operands:

k in range 0 to 2047

Operation:

(PC) + -> TOS,

k-> PC<10:0>,

(PCLATH<4:3>)-> PC<12:11>

Status Affected:

None

Description:

Call Subroutine. First, the 13-bit return address

(PC+1) is pushed onto the stack. The eleven bit

immediate address is loaded into PC bits

<10:0>. The upper bits of the PC are loaded

from PCLATH<4:3>. CALL is a two cycle

instruction.

Words:

1

Cycles:

2

Example 1:

Here:

call There

Before Instruction

PC = AddressHere

After Instruction

TOS = Address Here + 1

PC = Address There

Mid-range Instruction Set

631

CLRF

Clear f

Syntax:

[ label ] CLRF

f

Operands:

f in range 0 to 127

Operation:

00h ->f

1-> Z

Status Affected:

Z

Description:

The contents of register 'f' are cleared and

the Z bit is set.

Words:

1

Cycles:

1

Example 1:

clrf

reg1

Before Instruction:

reg1 = 0x5a

After Instruction:

reg1 = 0x00

Z = 1

Example 2:

Clrf

INDF

Before Instruction:

FSR = 0xc2

[FSR]= 0xAA

After Instruction:

FSR = 0xc2

[FSR] = 0x00

Z = 1

632

Appendix C

CLRW

Clear w

Syntax:

[ label ] CLRW

Operands:

None

Operation:

00h -> w

1-> Z

Status Affected:

Z

Description:

w register is cleared. Zero bit (Z) is set.

Words:

1

Cycles:

1

Example 1:

CLRW

Before Instruction:

w = 0x5A

After Instruction:

w

=

0x00

Z

=

1

Mid-range Instruction Set

633

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CLRWDT

Operands:

None

Operation:

00h -> WDT

0

-> WDT prescaler count,

1

-> TO

1

-> PD

Status Affected:

TO, PD

Description:

CLRWDT instruction clears the Watchdog

Timer. It also clears the prescaler

count of the WDT. Status bits TO and PD are

set. The instruction does not change the

assignment of the WDT prescaler.

Words:

1

Cycles:

1

Example 1:

CLRWDT

Before Instruction:

WDT counter= x

WDT prescaler = 1:128

After Instruction:

WDT counter=0x00

WDT prescaler count=0

TO = 1

PD = 1

WDT prescaler = 1:128

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