Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

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Mid-range Instruction Set

645

NOP

No Operation

Syntax:

[ label ] NOP

Operands:

None

Operation:

No operation

Status Affected:

None

Description:

No operation.

Words:

1

Cycles:

1

Example

nop

Before Instruction:

PC

=

$

fter Instruction:

PC

=

$

+ 1

646 Appendix C

OPTION

Load Option Register

Syntax:

[ label ] OPTION

Operands:

None

Operation:

(w) -> OPTION_REG

Status Affected:

None

Description:

The contents of the w register are loaded in the

OPTION_REG register. This instruction is

supported for code compatibility with

PIC16C5X products. Since OPTION_REG is a

Readable/writable register, code can directly

address it without using this instruction.

Words: 1

Cycles: 1

Example:

movlw b’01011100’

option

.

Mid-range Instruction Set

647

RETFIE

Return from Interrupt

Syntax:

[ label ] RETFIE

Operands:

None

Operation:

TOS -> PC,

1 -> GIE

Status Affected:

None

Description:

Return from Interrupt. The 13-bit address at the

Top of Stack (TOS) is loaded in the PC. The

Global Interrupt Enable bit, GIE (INTCON<7>),

Is automatically set, enabling Interrupts. This is

a two cycle instruction.

Words:

1

Cycles:

2

Example

retfie

After Instruction:

PC = TOS

GIE = 1

648 Appendix C

RETLW

Return with Literal in W

Syntax:

[ label ] RETLW k

Operands:

k in range 0 to 255

Operation:

k -> w;

TOS -> PC

Status Affected:

None

Description:

The w register is loaded with the eight bit literal

'k'. The program counter is loaded 13-bit

address at the Top of Stack (the return

address). This is a two cycle instruction.

Words:

1

Cycles:

2

Example

movlw

2

; Load w with desired

; Table offset

call

table

; When call returns w

; contains value stored

; in table

Table:

addwf

pc

; w = offset

retlw

.22

; First table entry

retlw

.23

; Second table entry

retlw

.24

.

.

.

retlw

.29

; Last table entry

Before Instruction:

w = 0x02

After Instruction:

w = .24

Mid-range Instruction Set

649

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

Operands:

None

Operation:

TOS -> PC

Status Affected:

None

Description:

Return from subroutine. The stack is POPed

and the top of the stack (TOS) is loaded into

the program counter. This is a two cycle

instruction.

Words:

1

Cycles:

2

Example

return

After Instruction: PC = TOS

650 Appendix C

RLF

Rotate Left f through Carry

Syntax:

[ label ] RLF f,d

Operands:

f in range 0 to 127

d is either 0 or 1

Operation:

See description below

Status Affected:

C

Description:

The contents of register 'f' are rotated one bit to

the left through the Carry Flag. If 'd' is 0 the

result is placed in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Words:

1

Cycles:

1

Example 1

rlf

reg1,0

Before Instruction:

reg1 = 1110 0110

C = 0

After Instruction:

reg1 = 1110 0110

w =1100 1100

C =1

Example 2

rlf

INDF,1

Case 1:

Before Instruction:

w = xxxx xxxx

FSR = 0xc2

[FSR] = 0011 1010

C = 1

After Instruction:

w = 0x17

FSR = 0xc2

[FSR] = 0111 0101

C = 0

Case 2:

Before Instruction:

w = xxxx xxxx

FSR = 0xC2

[FSR] = 1011 1001

C = 0

After Instruction:

w = 0x17

FSR = 0xC2

[FSR] = 0111 0010

C = 1

Mid-range Instruction Set

651

RRF

Rotate Right f through Carry

Syntax:

[ label ] RRF f,d

Operands:

f in range 0 to 127

d is either 0 or 1

Operation:

See description below

Status Affected:

C

Description:

The contents of register 'f' are rotated one bit to

the right through the Carry Flag. If 'd' is 0 the

result is placed in the w register. If 'd' is 1 the

result is placed back in register 'f'.

Words:

1

Cycles:

1

Example 1

rrf

reg1,0

Before Instruction:

reg1= 1110 0110

w = xxxx xxxx

C = 0

After Instruction:

reg1= 1110 0110

w = 0111 0011

C = 0

Example 2

rrf

INDF,1

Case 1:

Before Instruction:

w = xxxx xxxx

FSR = 0xc2

[FSR] = 0011 1010

C = 1

After Instruction:

w = 0x17

FSR = 0xC2

[FSR] = 1001 1101

C = 0

Case 2:

Before Instruction:

w = xxxx xxxx

FSR = 0xC2

[FSR] = 0011 1001

C = 0

After Instruction:

w = 0x17

FSR = 0xc2

[FSR] = 0001 1100

C = 1

652 Appendix C

SLEEP

Syntax:

[ label ] SLEEP

Operands:

None

Operation:

00h -> WDT,

0

-> WDT prescaler count,

1

-> TO,

0

-> PD

Status Affected:

TO, PD

Description:

The power-down status bit, PD is cleared.

Time-out status bit, TO is set. Watchdog Timer

and its prescaler count are cleared. The

processor is put into SLEEP mode with the

oscillator stopped. The SLEEP instruction does

not affect the assignment of the WDT

prescaler.

Words:

1

Cycles:

1

Example:

SLEEP

Mid-range Instruction Set

653

SUBLW

Subtract w from Literal

Syntax:

[ label ] SUBLW k

Operands:

k in range 0 to 255

Operation:

k - (W) -> W

Status Affected:

C, DC, Z

Description:

The w register is subtracted (2’s complement

method) from the eight bit literal 'k'. The result

is placed in the w register.

Words:

1

Cycles:

1

Example 1

sublw 0x02

Case 1:

Before Instruction:

w = 0x01

C = x

Z = x

After Instruction:

w = 0x01

C = 1 if result +

Z = 0

Case 2:

Before Instruction:

w = 0x02

C = x

Z = x

After Instruction:

w = 0x00

C = 1 ; result = 0

Z = 1

Case 3:

Before Instruction:

w = 0x03

C = x

Z = x

After Instruction:

w = 0xff

C = 0 ; result -

Z = 0

Example 2

sublw myreg

Before Instruction:

w = 0x10

[myreg]

= 0x37

After Instruction

w

=

0x27

C

=

1 ;

result

+

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