Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf
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654 Appendix C
SUBWF |
Subtract w from f |
Syntax: |
[ label ] SUBWF f,d |
Operands: |
f in range 0 to 127 |
d is either 0 or 1 |
|
Operation: |
(f) - (W) -> destination |
Status Affected: |
C, DC, Z |
Description: |
Subtract (2’s complement method) w register |
from register 'f'. If 'd' is 0 the result is stored in |
|
the w register. If 'd' is 1 the result is stored |
|
back in register 'f'. |
|
Words: |
1 |
Cycles: |
1 |
Example 1
subwf reg1,1
Case 1: |
Before Instruction: |
reg1 = 3 |
w = 2 |
||
C = x |
||
Z = x |
||
After Instruction: |
reg1 = 1 |
|
w = 2 |
||
C = 1 ; result + |
||
Z = 0 |
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Case 2: |
Before Instruction: |
reg1 = 2 |
w = 2 |
||
C = x |
||
Z = x |
||
After Instruction: |
reg1 = 0 |
|
w = 2 |
||
C = 1 ; result = 0 |
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Z = 1 |
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Case 3: |
Before Instruction: |
reg1 = 1 |
w = 2 |
||
C = x |
||
Z = x |
||
After Instruction: |
reg1 = 0xff |
|
w = 2 |
||
C = 0 ; result is - |
||
Z = 0 |
Mid-range Instruction Set |
655 |
SWAPF |
Swap Nibbles in f |
Syntax: |
[ label ] SWAPF f,d |
Operands: |
f in range 0 to 127 |
d is either 0 or 1 |
|
Operation: |
(f<3:0>) -> destination<7:4>, |
(f<7:4>) -> destination<3:0> |
|
Status Affected: |
None |
Description: |
The upper and lower nibbles of register 'f' are |
exchanged. If 'd' is 0 the result is placed in w |
|
register. If 'd' is 1 the result is placed in register |
|
'f'. |
|
Words: |
1 |
Cycles: |
1 |
Example 1
swapf reg,0 |
||
Before Instruction: |
reg1 = |
0xa5 |
After Instruction: |
reg1 = |
0xa5 |
W = 0x5a |
||
Example 2 |
||
Swapf INDF,1 |
|
Before Instruction: |
w = 0x17 |
FSR = 0xc2 |
|
[FSR] = 0x20 |
|
After Instruction: |
w = 0x17 |
FSR = 0xC2 |
|
[FSR] = 0x02 |
|
Example 3 |
swapf reg,1
Before Instruction: |
reg1 |
= |
0xa5 |
After Instruction: |
reg1 |
= |
0x5a |
656 Appendix C
TRIS |
Load TRIS Register |
|
Syntax: |
[ label ] TRIS f |
|
Operands: |
f in range 5 to 7 |
|
Operation: |
(W) -> TRIS register f; |
|
Status Affected: |
None |
|
Description: |
The instruction is supported for code |
|
compatibility with the PIC16C5X products. |
||
Since TRIS registers are readable and writable, |
||
code can address these registers directly |
||
Words: |
1 |
|
Cycles: |
1 |
|
Example |
||
movlw |
B'00000000' |
|
tris |
PORTB |
|
Mid-range Instruction Set |
657 |
XORLW |
Exclusive OR Literal with W |
||
Syntax: |
[ label] XORLW k |
||
Operands: |
k in range 0 to 255 |
||
Operation: |
(w).XOR. k -> W |
||
Status Affected: |
Z |
||
Description: |
The contents of the w register are XOR’ed with |
||
the eight bit literal 'k'. The result is placed in the |
|||
w register. |
|||
Words: |
1 |
||
Cycles: |
1 |
||
Example 1 |
|||
xorlw |
b’10101111’ |
||
Before Instruction: |
w = 1011 0101 |
||
After Instruction : |
w = 0001 1010 |
||
Z = 0 |
|||
Example 2 |
|||
xorlw |
myreg |
||
Before Instruction: |
w = 0xaf |
||
[Myreg] = 0x37 |
|||
After Instruction: |
w = 0x18 |
||
Z = 0 |
|||
658 Appendix C
XORWF |
Exclusive OR w with f |
||
Syntax: |
[ label ] XORWF f,d |
||
Operands: |
f in range 0 to 127 |
||
d is either 0 or 1 |
|||
Operation: |
(W).XOR. (f) -> destination |
||
Status Affected: |
Z |
||
Description: |
Exclusive OR the contents of the w register |
||
with register 'f'. If 'd' is 0 the result is stored in |
|||
the w register. If 'd' is 1 the result is stored back |
|||
in register 'f'. |
|||
Words: |
1 |
||
Cycles: |
1 |
||
Example 1 |
|||
xorwf |
reg,1 |
||
Before Instruction: |
w = 1011 0101 |
||
reg = 1010 1111 |
|||
After Instruction: |
reg = 0001 1010 |
||
w = 1011 0101 |
|||
Example 2 |
|||
xorwf |
reg,0 |
||
Before Instruction |
w = 1011 0101 |
||
reg = 1010 1111 |
|||
After Instruction: |
reg = 1010 1111 |
||
w = 0001 1010 |
|||
Example 3 |
|||
xorwf |
INDF,1 |
||
Before Instruction: |
w = 1011 0101 |
||
FSR = 0xc2 |
|||
[FSR] = 1010 1111 |
|||
After Instruction: |
w = 1011 0101 |
||
FSR = 0xc2 |
|||
[FSR] = 0001 1010 |
|||