Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

; Address of LCD line 1 in constant LCD_1 line1:

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;ON ENTRY:

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line2:

The entire program, named TTYUsart, is found in the book’s online software package.

14.4.2 RS-232-C Communications on the 16F87x

The second alternative for protocol-compliant communications is using a PIC that provides hardware support for the standard. The 16F84, our workhorse in this book, contains no such facilities. However, other midrange PICs do provide hardware support to one or several serial communications protocols.

For the examples that follow, we have selected what is perhaps the second most popular PIC of the midrange family (after the 16F84): the 16F87x. The architecture and basic programming facilities of the 16F87x PIC family were discussed in Chapter 8. At this time, we should recall that 16F87x includes the PIC 16F873, 16F874, 16F876, and 16F877. For our sample programs we have selected the 16F877 since it is the most powerful one of the group. The 16F877 has an operating frequency of up to 20Mhz, 8K of flash program memory, 368 bytes of data memory, 256 bytes of EEPROM, 5 input/output ports, and contains two modules for serial communications: a Master Synchronous Serial Port and a Universal Synchronous/Asynchronous Receiver and Transmitter. We focus on the USART module and leave the MSSP for the chapter on EEPROM programming.

The 16F87x USART Module

The Universal Synchronous Asynchronous Receiver Transmitter (USART) module in the 16F87X family is also known as a Serial Communications Interface, or SCI. The USART module is useful in communicating with devices and systems that support RS-232-C communications, including computers and terminals. It can be configured as an asynchronous full-duplex device, as a synchronous half-duplex master, or as a synchronous half-duplex slave. In the synchronous mode, the USART module is used mostly in communicating with analog-to-digital and digital-to-analog integrated circuits or for accessing serial EEPROMS. Both of these functions are discussed in later chapters.

Five registers relate to USART operation in the 16F877: RCSTA, TXREG, RCREG,

TXSTA, and SPBRG. The first three are located in bank 0 and the second two in bank 1. TXSTA is the Transmit Status and Control register and the RCSTA the Receive Status and Control register. Figure 14-14 shows the bitmap for the TXSTA register located at address 0x98 in bank 1.

The RCSTA register contains control and status bits for the receive function. The register is found at address 0x18 in bank 0. Figure 14-15 (in the following page) is a bitmap of the RCSTA register.

The USART Baud Rate Generator

In the USART emulation programs for the 16F84 we were forced to approximate the RS-232-C baud rate with the system clock. The USART module in the 16F87X PICs contains its own baud rate generator, but it is also dependent on the system clock.

Setting the baud rate in the USART module consists of manipulating the Baud Rate Generator (BRG) unit. The BRG is a dedicated 8-bit generator that supports both the asynchronous and synchronous modes. The SPBRG is an 8-bit register that controls the rate of a dedicated timer. In the asynchronous mode, the bit labeled BRGH in the TXSTA register (see Figure 14-14) also relates to the baud rate since it allows setting either slow-speed or high-speed baud rate. The baud-rate-speed-se- lect bit is inactive in the synchronous mode.

Figure 14-14 Bitmap of the TXSTA Register

The formula for computing the baud rate takes into account the system oscillator speed (Fosc), the setting of the Baud-Rate-Speed-Select bit (BRGH), which is set for the high-speed mode and cleared for slow-speed, and also the setting of the SYNC bit in TXSTA register, which selects either asynchronous or synchronous mode. The formula is as follows:

= Fosc

ABR

S(x +1)

where ABR represent the Asynchronous Baud Rate, x is the value in the SPRGB regis-

ter (range 0 to 255), S is 64 in the high-speed mode (BRGH bit is 1) and 16 in the slow

speed mode (BRGH bit is 0). Solving the formula in terms of the value to be placed in

the SPRGB register we get:

In this case, the value to store in the SPRGB register is 25. The actual baud rate can now be calculated using the first equation, as follows:

The percent error in the baud rate can be estimated by dividing the difference between the desired and the actual baud rate by the desired baud rate. The percent error is 0.16.

16F87x USART Asynchronous Transmitter

The USART in the 16F87x PICs uses a non-return-to-zero format, consisting of one start bit, eight or nine data bits, no parity, and one stop bit. In compliance with RS-232-C the USART transmits and receives the least significant bit first. Transmitter and receiver units are functionally independent but use the same data format and baud rate.

Although parity is not directly supported by the hardware, it can be implemented in software by using the ninth data bit. Figure 14-16 shows the 16F87x registers related to asynchronous transmission.

Figure 14-16 16F87x Registers used in Asynchronous Transmission

The transmitter function also uses the Transmit Shift register (TSR), which is not mapped in memory and is thus not accessible to code. TSR obtains its data from the read/write transmit buffer, named TXREG, which is loaded in software after the stop bit is received. Then TXREG transfers the data to TSR and becomes empty. At this time the TXIF flag bit is set. An interrupt related to the TXIF bit is enabled/disabled by setting/clearing the TXIE enable bit in the PIE1 register. However, the TXIF flag bit is set regardless of the state of the TXIE enable bit. The TXIF flag is reset automatically when new data is loaded into TXREG.

While the TXIF flag indicates the status of TXREG, the TRMT bit, in TXSTA, reflects the status of TSR. TRMT is set when TSR is empty. This is a read-only bit. No interrupts are linked to the TRMT bit, so the program has to poll this bit to determine if TSR is empty. Transmission is enabled by setting the TXEN bit in TXSTA. The actual transmission does not occur until TXREG is loaded with data and the baud rate generator (BRG) has produced a clock beat. Alternatively, transmission can be started by loading TXREG and then setting the TXEN enable bit.

When transmission starts, the (not accessible) TSR register usally is empty. Thereafter, transferring data to TXREG results in a transfer to TSR, which then produces an empty TXREG. This mechanism makes possible the back-to-back transfer. Clearing the TXEN enable bit during transmission aborts the transmission. This action also resets the transmitter and sets the TX/CK pin high.

16F87x USART Asynchronous Receiver

When Asynchronous mode is selected by setting the SYNC bit in TXSTA, then reception can be enabled by setting the CREN bit

In the RCSTA register. Figure 14-17 shows the registers related to asynchronous reception.

Figure 14-17 Registers used in Asynchronous Reception

The main operational register is the RSR (Receive Shift Register), which, like TSR, is not accessible to application software. As soon as the stop bit is detected in the RX/TX pin, the received data in RSR is transferred to RCREG if it is empty. In this case, the RCIF flag bit is set. The interrupt linked to the RCIF flag is enabled or disabled by means of the RCIE in the PIE1 register. The RCIF flag bit is read-only and can be cleared only by hardware; this happens when the RCREG register has been read and is empty.