Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

1.The context is saved. This includes, but is not limited to, the status register, the w register, the PCLATH register, and the FSR register.

2.Code tests for received data by checking the RCIF bit in the PIR1 register. If this bit is clear the interrupt did not originate in received data.

3.Code can also check if the interrupt enable bit (RCIE) is set in the RCIE register. If not enabled the interrupt is related to serial data.

4.The handler usually checks two possible errors during reception: overflow and framing error. The first one by checking the OERR bit and the second one by checking the FERR bit, both in the RCSTA register. If reception errors have taken place, the handler takes appropriate action.

5.If no error is detected then the received data can be retrieved from the RCREG.

6.On exit the interrupt handler restores the context and issues the retfie instruction.

The following code fragment lists the variables and processing routine for an interrupt handler for serial data reception:

=====================================================

; variables in PIC RAM

;===================================================== ; Local variables

;Communications variables errorFlags

;Temporary storage used by interrupt handler tempW

tempStatus tempPclath tempFsr endc

;============================================================

;============================================================ ; interrupt handler for received characters ;============================================================ ;============================================================ IntServ:

;|__________________ (RCIF) USART receive interrupt

;|__________________ (RCIE) Receive interrupt enable

;==============================

;received data ;==============================

;Routine to handler received data. Overrun and framing

;errors are detected and remembered in the variable

;errorFlags, as follows:

;Test for overrun and framing errors.

;Bit 1 (OERR) of the RCSTA register detects overrun

;Bit 2 (FERR) of the RCSTA register detects framing error

;At this point no error was detected

;Received data is in the USART RCREG register

;==========================

;error handlers ;==========================

;Errors are returned as bits in the errorFlags register

;A pushbutton switch is in the 16F84 RESET line

;

;Communications parameters:

;Timer channel TMR0 is used for synchronizing data

;transmission. The timer runs at the maximum rate of

;256 cycles per iteration. In a 4Mhz system the

;timer rate is 1Mhz, thus the bit rate is

;which is approximately 3,906 microseconds per bit.

;===========================

;switches

;===========================

; Switches used in __config directive:

;_PWRTE_OFF

;|

;|_____ * indicates setup values presently selected

;========================= ; setup and configuration ;=========================

;============================================================

; M A C R O S

;============================================================ ; Macros to select the register banks