Файл: Microcontroller Programming. Thi Micro Chip PIC (Julio Sanchez, 2007).pdf

RCREG is double-buffered, meaning that it is possible for two bytes of data to be started simultaneously while a third byte begins shifting to RSR. If the stop bit is detected while RCREG is not empty, then the overrun error bit (OERR) is set in

RCSTA. RCREG operates in first-in-first-out order. When it is read twice the two bytes are retrieved in this order.

The overrun error bit (OERR) inhibits transfer from RSR into RCREG; therefore, it is important to clear this bit once the error is detected. The framing error bit (FERR) in the RCSTA register is set if a stop bit is not detected.

The following steps are followed in initializing and executing asynchronous reception:

1.The SPBRG register is set up for the selected baud rate.

2.Asynchronous reception is enabled by clearing the SYNC bit in the TXSTA register and setting the SPEN bit in the RCSTA register.

3.To enable the receive data interrupt, the RCIE, GIE, and PEIE bits must be set.

4.Reception is activated by setting the CREN bit in RCSTA.

5.When reception has concluded, the RCIF bit in the PIE1 register is set. At that time, an interrupt is generated if the RCIE bit was set.

6.Received data is retrieved by reading RCREG.

7.If any error occurred the CREN bit must be cleared.

PIC-to-PC RS-232-C Communications Circuit

To demonstrate serial communications with the RS-232-C protocol we developed a circuit consisting of a 4-by-4 keypad and a 2-line by 20-character LCD display. Characters typed on the keypad are converted to ASCII codes for the hexadecimal digit set, that is, the numeral digits and the letters A through F. When a key is pressed, the corresponding ASCII code is displayed in the LCD and transmitted through the serial port to a PC application. Characters received through the serial line are displayed on the LCD. Figure 14-18 (in the following page) is a wiring diagram of the circuit.

The program SerComLCD demonstrates the circuit in Figure 14-18:

16F877 PIC Initialization Code

The following code fragment shows the initialization of the UART module in the 16F877 PIC for 2400 baud, 8 bits, no parity, and one stop bit. No interrupts are used in this example.

;==============================================================

;==============================================================

;Initialize serial port for 2400 baud, 8 bits, no parity,

;1 stop

InitSerial:

; Bits 6 and 7 of Port C are multiplexed as TX/CK and RX/DT

;Where x is the value in the SPBRG register and S is 64 if the

;high baud rate select bit (BRGH) in the TXSTA control register

;is clear, and 16 if the BRGH bit is set. For setting to 9600

;baud using a 4Mhs oscillator at a high-speed baud rate the

;formula is:

;|______________________ CSRC Clock Source Select

;|_____________________ SPEN Serial Port Enable

USART Receive and Transmit Routines

The transmit data routine is quite simple. Code checks the TXIF bit in PIR1. If the bit is set, data is transmitted by storing the data byte in TXREG. The following procedure performs the required operations.

;==============================

;transmit data ;==============================

;Test for Transmit Register Empty and transmit data in w SerialSend:

busyWait:

Receiving data is more complicated than transmitting it. One of the reasons is that code must test for and handle several possible errors that can occur during reception. The following code fragment shows the local variables and processing required for simple data reception.

;=====================================================

; variables in PIC RAM

;===================================================== ; Local variables

; Communications variables

;=========================================================== ; USART receive data procedure ;===========================================================

;Procedure to test line for data received and return value

;in w. Overrun and framing errors are detected and

;remembered in the variable errorFlags, as follows:

;Bit 5 (RCIF) of the PIR1 Register is clear if the USART

;receive buffer is empty. If so, no data has been received

;At this point data has been received. First eliminate

;possible errors: overrun and framing.

;Bit 1 (OERR) of the RCSTA register detects overrun

;Bit 2 (FERR( of the RCSTA register detects framing error

; At this point no error was detected

;==========================

;error handlers ;==========================

;Overrun error detected OverErr:

The procedures listed previously are from the program SerComLCD in the book’s online software. The applicable circuit is shown in Figure 14-18.

The USART Receive Interrupt

Polled routines for serial communications are adequate when the application does little else but check transmission lines. If the application has other tasks to perform, polled routines can waste processing time and even lose data. In this sense, the send function is usually less critical. An application can typically determine when to send data and have available all the data when the send operation activates. This is often not the case in receiving data, especially in applications that execute full-duplex.

A practical solution is to use interrupts for receiving characters through the serial line. The 60F87x includes facilities for implementing interrupt routines by both the send and the receive functions. To enable interrupts for the USART receive operation the following preparatory steps are necessary:

1.Peripheral and global interrupts must be enabled by setting bits 6 and 7 of the INTCON register.

2.The receive interrupt must be enabled by setting the RCIF bit in the PIE1 register.

The handler for the serial reception interrupt usually performs the following functions: