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Chapter 14

;Routine to handler received data. Overrun and framing

;errors are detected and remembered in the variable

;errorFlags, as follows:

;

7

6

5 4

3

2

1 0

<== errorFlags

;

not

used

——

|

|___

overrun error

;

|______ framing error

Bank0

; Select bank 0

;Test for overrun and framing errors.

;Bit 1 (OERR) of the RCSTA register detects overrun

;Bit 2 (FERR) of the RCSTA register detects framing error

btfsc

RCSTA,OERR

; Test

for overrun error

goto

OverErr

;

Error handler

btfsc

RCSTA,FERR

;

Test

for framing error

goto

FrameErr ; Error handler

;At this point no error was detected

;Received data is in the USART RCREG register

movf

RCREG,w

; Received data into w

call

send8

; Display in LCD

call

LCDscroll

; Scroll at end of line

; Clear error flags

clrf

errorFlags

goto

IntExit

;==========================

;error handlers ;==========================

;Errors are returned as bits in the errorFlags register

;

7

6 5 4

3

2

1 0 <=

errorFlags

;

—-

not used

—-

|

|____ overrun error

;

|_______

framing error

; Error responses to be made by main code

OverErr:

bsf

errorFlags,0

; Bit 0 is overrun error

; Reset system

bcf

RCSTA,CREN

; Clear continuous receive bit

bsf

RCSTA,CREN

; Set to re-enable reception

goto

IntExit

FrameErr:

bsf

errorFlags,1; Bit 1 is framing error

movf

RCREG,W

; Read and throw away bad data

;==============================

;

interrupt handler exit

;==============================

IntExit:

Bank0

movf

tempFsr,w

; Recover FSR value

movwf

FSR

; Restore in register

movf

tempPclath,w

; Recover PCLATH value

movwf

PCLATH

; Restore in register


Communications

457

movf

tempStatus,W

; Recover STATUS

movwf

STATUS

; Restore in register

swapf

tempW,F

; Swap file register in itself

swapf

tempW,W

; Restore in register

retfie

end


Chapter 15

Data EEPROM Programming

EEPROM stands for Electrically-Erasable Programmable Read-Only Memory. EEPROM is used in computers and digital devices as non-volatile storage. EEPROM is found in flash drives, BIOS chips, and in flash memory and EEPROM data storage memory in PICs and other microcontrollers.

EEPROM memory can be erased and programmed electrically without removing the chip. EPROM, the predecessor of EEPROM, required chip removal from the circuit and ultraviolet light exposure in order to erase the chip. In addition, EPROM requires higher-than-TTL voltages for reprogramming while EEPROM does not.

The PIC programmer regards EEPROM data memory as onboard EEPROM memory and EEPROM memory ICs as separate circuit components. In general, EEPROM elements are classified according to their electrical interfaces into serial and parallel. In this context we deal only with serial EEPROMs. The storage capacity of Serial EEPROMs ranges from a few bytes to 128 kilobytes. In PIC technology, the typical use of serial EEPROM onboard memory and EEPROM ICs is to store passwords, codes, configuration settings, and other information to be remembered after the system is turned off. For example, a PIC-based automated environment sensor can use EEPROM memory (onboard or independent) to store daily temperatures, humidity, air pressure, and other values. Later, this information could be downloaded to a PC and the EEPROM storage erased and reused for new data. In personal computers, EEPROM memory is used to store BIOS code and other system data.

Some early EEPROM could only be erased and rewritten about 100 times, while modern EEPROM tolerate thousands of erase-write cycles. EEPROM memory is different from RAM (Random Access Memory) in that RAM can be rewritten millions of times. Also, RAM is generally faster to write than EEPROM and considerably cheaper per unit of storage. On the other hand, RAM is volatile, so the contents are lost when power is removed.

PICs use EEPROM-type memory internally as flash program memory and as data memory. EEPROM data memory is covered in this chapter. Serial EEPROM memory

459

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Chapter 15

is available as separate ICs that can be placed on the circuit board and accessed through PIC ports. For example, the Microchip 24LC04B EEPROM IC is a 4K electrically erasable PROM with a 2-wire serial interface that follows the I2C convention. Programming serial EEPROM ICs is also covered in this chapter.

15.0 PIC Internal EEPROM Memory

Some PICs contain internal EEPROM data memory that is accessible to code. The amount of memory and the access mechanism varies from PIC to PIC. In fact, the mapping and access mechanisms varies even in devices belonging to the same family. In the sections that follow, we describe EEPROM data memory in the context of two different PICs of the mid-range family: the 16F84 and the 16F877.

15.0.1 EEPROM Programming on the 16F84

The 16F84 and 16F84A contain 64 bytes of EEPROM data memory. This memory is both readable and writable during normal operation. It is not mapped in the register file space, but is indirectly addressed through the Special Function Registers EECON1, EECON2, EEDATA, and EEADR. The address of EEPROM memory starts at location 0x00 and extends to the maximum contained in the PIC, in this case, 0x3f. The following registers relate to EEPROM operations:

1.EEDATA holds the data byte to be read or written.

2.EEADR contains the EEPROM address to be accessed by the read or write operation.

3.EECON1 contains the control bits for EEPROM operations.

4.EECON2 protects EEPROM memory from accidental access. This is not a physical register.

Figure 15-1 shows the bitmap of the EECON1 register in the 16F84.

The CPU continues to access EEPROM memory even if the device is code protected, but in this case the device programmer can not access EEPROM memory.

Reading EEPROM Data Memory on the 16F84

Reading an EEPROM data memory location in the 16F84 requires the following operations:

1.Bank 0 is selected and the address of the memory to be read is stored in the EEADR register.

2.Bank 1 is selected and the RD bit is set in the EECON1 register.

3.Bank 0 is selected and data is read from the EEDATA register.

The following procedure returns in the w register the data stored at the specified EEPROM memory address.

;==============================

;read EEPROM 16F84 ;==============================

;Procedure to read EEPROM memory. Address of memory

;location to read is stored in local register EEMemAdd


Data EEPROM Programming

461

bit 7

bit 0

EECON1

EEIF

WRERR

WR

RD

bit 7-5

Unimplemented: Read as '0'

bit 4 EEIF:

EEPROM

Write Operation Interrupt Flag bit

1

=

The write operation completed

(must be cleared in software)

0

=

The write operation is not complete

or has not been started

bit 3 WRERR: EEPROM

Error Flag bit

1

=

write operation terminated prematurely

0

=

The write operation completed

bit 2 WREN:

EEPROM

Write Enable bit

1

=

Allows write cycles

0

=

Inhibit write to the EEPROM

bit 1 WR:

Write Control bit

1

=

Initiates a write cycle. Bit is

cleared once write is complete.

Can only be set in software.

0

=

Write cycle to the EEPROM is complete

bit 0 RD:

Read

Control bit

1

=

Initiates an EEPROM read. Bit is

cleared in hardware. Can only be set

in software.

0

=

Does not initiate an EEPROM read

Figure 15-1 16F84 EECON1 Register Bit Map

; On exit: read data in w EERead:

bcf

STATUS,RP0

; Bank

0

movf

EEMemAdd,w

; Address to w

movwf

EEADR

; w to

address register

bsf

STATUS,RP0

; Bank

1

bsf

EECON1,RD

; EE Read

bcf

STATUS,RP0

; Bank

0

movf

EEDATA,w

; W = EEDATA

return

16F84 EEPROM Data Memory Write

Writing to 16F84 EEPROM data memory consists of the following operations:

1.Bank 0 is selected and the address of the desired memory location is stored in the EEADR register.

2.The value to be written is stored in the EEDATA register.

3.Bank 1 is selected, interrupts are disabled, and the write enable bit (WREN) is set in the EECON1 register.


462

Chapter 15

4.The special values 0x55 and 0xaa are written consecutively to the EECON2 register.

5.The WR bit is set in the EECON1 register. The EEPROM write takes place automatically after the WR bit is set.

6.Interrupts are re-enabled and bank 0 is selected.

The following procedure shows the processing for the EEPROM write.

;==============================

;write EEPROM ;==============================

;Procedure to write asc1 byte to EEPROM memory

;Address to write stored in local register EEMemAdd

;Data byte to write is in local register EEByte EEWrite:

;Load byte to write into EE data register

movf

EEByte,w ; Data to w

movwf

EEDATA ; Write

; Set write address in EE address register

movf

EEMemAdd,w

; Address to w

movwf

EEADR

; w to address register

; Write data to EEPROM memory

bsf

STATUS,RP0

; Bank 1

bcf

INTCON,GIE

; Disable INTs.

bsf

EECON1,WREN

; Enable Write

movlw

0x55

; Code # 1

movwf

EECON2

; Write 0x55

movlw

0xaa

; Code # 2

movwf

EECON2

; Write 0xaa

bsf

EECON1,WR

; Set WR bit

; Write operation now takes place automatically

bsf

INTCON,GIE

; Re-enable interrupts

bcf

STATUS,RP0

; Bank 0

return

Microchip documentation recommends that critical applications should verify the write operation by reading EEPROM memory after the write operation has taken place in order to make sure that the correct value was stored.

16F84 EEPROM Demonstration Program

The program EECounter, in the book’s online software, is a demonstration of EEPROM memory access on the 16F84 PIC. The program keeps track of the number of times that the code has executed by storing each iteration in EEPROM data memory. The program uses the circuit shown in Figure 15-2 (see following page).

The EECounter program increments the value stored at EEPROM address 0x00 at every iteration and displays the result on the first LCD line. The following procedure is used to convert the binary value in EEPROM to 3 ASCII digits for display.