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Data EEPROM Programming

+5V

R/W

RESET

R=10K

1

RS

18

E

RA2

RA1

2

17

3

RA3

RA0

16

4

RA4/TOCKI

OSC1

15

MCLR

OSC2

5

16F84

14

+5V

Vss

Vdd

6

13

RB0/INT

RB7

7

12

8

RB1

RB6

11

RB2

RB5

9

10

RB3

RB4

463

Osc 4Mhz

LCD

2 rows x 16

14

RS

E

R/W

+5V

1

HD44780

Figure 15-2 Circuit for 16F84 EEPROM Demonstration Program

;==============================

;binary to ASCII decimal

;conversion ;==============================

;ON ENTRY:

;w register has binary value in range 0 to 255

;ON EXIT:

;output variables asc100, asc10, and asc1 have

;three ASCII decimal digits

;Routine logic:

;The value 100 is subtracted from the source operand

;until the remainder is < 0 (carry cleared). The number

;of subtractions is the decimal hundreds result. 100 is

;then added back to the subtrahend to compensate

;for the last subtraction. Now 10 is subtracted in the


464

Chapter 15

;same manner to determine the decimal tenths result.

;The final remainder is the decimal units result.

;Variables:

;

inNum

storage for source operand

;asc100 storage for hundreds position result

;

asc10

storage for tenth position result

;

asc1

storage for unit position result

;

thisDig

Digit counter

bin2asc:

movwf

inNum

; Save copy of source value

clrf

asc100

; Clear hundreds storage

clrf

asc10

; Tens

clrf

asc1

; Units

clrf

thisDig

sub100:

movlw

.100

subwf

inNum,f

; Subtract 100

btfsc

STATUS,C

; Did subtract overflow?

goto

bump100

; No. Count subtraction

goto

end100

bump100:

incf

thisDig,f

;increment digit counter

goto

sub100

; Store 100th digit

end100:

movf

thisDig,w

; Adjusted digit counter

addlw

0x30

; Convert to ASCII

movwf

asc100

; Store it

; Calculate tenth position value

clrf

thisDig

; Adjust minuend

movlw

.100

; Minuend

addwf

inNum,f

; Add value to minuend to

; compensate for last

; operation

sub10:

movlw

.10

subwf

inNum,f

; Subtract 10

btfsc

STATUS,C

; Did subtract overflow?

goto

bump10

; No. Count subtraction

goto

end10

bump10:

incf

thisDig,f

; Increment digit counter

goto

sub10

; Store 10th digit

end10:

movlw

.10

addwf

inNum,f

; Adjust for last subtraction


Data EEPROM Programming

465

movf

thisDig,w

; Digit counter contents

addlw

0x30

; Convert to ASCII

movwf

asc10

; Store it

; Calculate and store units digit

movf

inNum,w

; Store units value

addlw

0x30

; Convert to ASCII

movwf

asc1

; Store digit

Return

15.0.2 EEPROM Programming on the 16F87x

The 16F87x PICs contain 128 or 256 bytes of EEPROM data memory. As in the 16F84, this memory is both readable and writable during normal operation. It is not mapped in the register file space but is indirectly addressed through Special Function Registers, as described later in this section.

In the 16F87x PICs both data EEPROM and flash Program Memory are readable and writable during normal operation. For data EEPROM memory, read and write operations take place one byte at a time. The write operation performs an erase-then-write cycle. No bulk erase function is available to user code.

The following Special Function Registers are used in 16F87x EEPROM data read and write operations:

1.EEDATA holds the data byte to be read or written.

2.EEADR contains the EEPROM address to be accessed by the read or write operation.

3.EECON1 contains the control bits for EEPROM operations.

4.EECON2 protects EEPROM memory from accidental access. This is not a physical register.

EEPROM data memory read and write operations do not interfere with normal PIC operations. The 16F873 and 16F874 PICs have 128 bytes of EEPROM data memory. These ICs require that the most-significant-bit of EEADR remains clear. The EEPROM data memory on these devices does not wrap around; that is, accessing EEPROM address 0x80 does not map to 0x00. The 16F876 and 16F877 devices have 256 bytes of EEPROM data memory. In these devices all 8-bits of the EEADR are used. Figure 15-3 (in the following page) is a bit map of the EECON1 register in the 16F87x.

The 16F87x EECON1 register contains one additional bit that is not present in the 16F84, named EEPGD. This bit determines if the EEPROM operation accesses program or data memory. When clear, any subsequent operations relate to EEPROM data. Otherwise, the operation accesses program memory. Read operations only require the RD bit, which initiates the read from the selected memory location. The RD bit is automatically cleared at the end of the read operation. The data in the selected memory location can be read in the EEDATA register as soon as the RD bit is set.


466

Chapter 15

bit 7

bit 0

EEPGD

EEIF

WRERR

WR

RD

bit 7 EEPGD: Program/Data EEPROM select bit

1

= EEPROM program memory access

0

= EEPROM data memory access

bits 6-5

Unimplemented: Read as '0'

bit 4 EEIF:

EEPROM

Write Operation Interrupt Flag bit

1

= The write operation completed

(must be cleared in software)

0

= The write operation is not complete

or has not been started

bit 3 WRERR: EEPROM

Error Flag bit

1

=

write operation terminated prematurely

0

=

The write operation completed

bit 2 WREN:

EEPROM

Write Enable bit

1

=

Allows write cycles

0

=

Inhibit write to the EEPROM

bit 1 WR:

Write Control bit

1

= Initiates a write cycle. Bit is

cleared once write is complete.

Can only be set in software.

0

= Write cycle to the EEPROM is complete

bit 0 RD:

Read

Control bit

1

= Initiates an EEPROM read. Bit is

cleared in hardware. Can only be set

in software.

0

= Does not initiate an EEPROM read

Figure 15-3 16F87x EECON1 Register Bitmap

Write operations require two control bits, WR and WREN, and two status bits, WRERR and EEIF. The purpose of these bits is shown in Figure 15-3. Since the WREN bit enables or disables the write operation, it must be set before executing a write. The WR bit is used to initiate the write operation. This bit is automatically cleared at the end of the write. The interrupt flag bit EEIF can be use to detect when the memory write completes. The EEIF bit must be cleared by software before setting the WR bit. As soon as the WREN bit and the WR bit have been set, the desired memory address in EEADR is erased and the value in EEDATA written to the selected address.

The WRERR bit indicates when the 16F87x has been reset during a write operation. This bit should be cleared after power-on reset. The WRERR bit is set when a write operation is interrupted by a MCLR reset, or a Watchdog time-out.


Data EEPROM Programming

467

Reading EEPROM Data Memory on the 16F87x

Reading an EEPROM data memory location in the 16F87x requires the following operations:

1.Write the address of the EEPROM location to be read to the EEDATA register. The address should be within the device’s memory capacity.

2.The EEPGD bit in the EECON1 registered is cleared so as to access data memory.

3.The RD bit in the EECON1 register is set to start the read operation.

4.The data can now be read from the EEDATA register.

The following code fragment shows reading EEPROM data memory in the 16F877 PIC:

;==============================

;16F877 read EEPROM data ;==============================

;Procedure to read EEPROM on-board memory

;ON ENTRY:

;Address of EEPROM memory location to read is stored in

;local register EEMemAdd

;ON EXIT:

;Read data in w

EERead:

Bank2

movf

EEMemAdd,W

; EEPROM address

movwf

EEADR

; to read from

Bank3

bcf

EECON1,EEPGD

; Point to Data memory

bsf

EECON1,RD

; Start read

Bank2

movf

EEDATA,W

; Data to w register

Bank0

Return

Writing to EEPROM Data Memory in the 16F87x

Writing to 16F87x EEPROM data memory is more complex than on the 16F84 and much more complex than the read operation. The process consists of the following operations:

1.Make sure that a previous write operation is not in progress. This step is not necessary if write completion is checked at the end of the write routine.

2.The address to be accessed is stored in the EEADR register. Code should make certain that the address is within the device’s range.

3.The data to be written is stored in the EEDATA register.

4.The EEPGD bit in the EECON1 register is cleared to select data memory access.

5.The WREN bit in the EECON1 register is set to enable the write function.