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Contents XIII
6.3 Distinctive Features of the General-Purpose Timer of HC11 . . . . . . . 69 6.3.1 The Control and Status Registers of the HC11 Timer . . . . . . 69
6.3.2Exercises Regarding the Use of the General-Purpose Timer
of HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4 Distinctive Feature of the Timer of the AVR Microcontrollers . . . . . 75 6.4.1 The 8-Bit Timer/Counter Timer0 . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.2 The 16-Bit Timer/Counter Timer1 . . . . . . . . . . . . . . . . . . . . . . 76 6.4.3 Synopsis of the Timer I/O Registers of AT90S8115 . . . . . . . . 78 6.4.4 Summary of the Unique Features of the AVR Timer . . . . . . . 79 6.4.5 Exercises Regarding the Use of AVR Timers . . . . . . . . . . . . . 79 6.5 Distinctive Features of the Timer System of the 8051 Microcontrollers 81 6.5.1 The Control and Status Registers of the Timer . . . . . . . . . . . . 82 6.5.2 Description of the Timer Operating Mode 0 . . . . . . . . . . . . . . 83 6.5.3 Description of the Timer Operating Mode 1 . . . . . . . . . . . . . . 83 6.5.4 Description of the Timer Operating Mode 2 . . . . . . . . . . . . . . 84 6.5.5 Description of the Timer Operating Mode 3 . . . . . . . . . . . . . . 84 6.5.6 Using Timer1 as a Baud Rate Generator . . . . . . . . . . . . . . . . . 85 6.5.7 Exercises for Programming the 8051 Timer . . . . . . . . . . . . . . 85
6.6 PWM Timers. Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.7 Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.7.1 The Watchdog of HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.7.2 The Watchdog of AT90S8515 . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7 Interfacing to Analog Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.1 In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 The Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.3 The General Structure of the A/D Converter Subsystem . . . . . . . . . . . 95 7.4 The A/D Converter of the HC11 Family of Microcontrollers . . . . . . . 96 7.5 Exercises on Programming the A/D Converter of HC11 . . . . . . . . . . . 98 7.6 The A/D Converter of the AVR Microcontrollers . . . . . . . . . . . . . . . . 100 7.7 Exercises on Programming the A/D Converter AT90S8535 . . . . . . . . 101 7.8 Digital-to-Analog Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.8.1 The Principles of the D/A Conversion . . . . . . . . . . . . . . . . . . . 102 7.8.2 Exercise on Using MX7224 . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8 Using the Internal EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.1 In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.2 Overwiew of the EEPROM Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.3 The EEPROM Memory and the CONFIG Register of HC11 . . . . . . . 107 8.3.1 The Registers Controlling the EEPROM of HC11 . . . . . . . . . 108 8.3.2 Software Routines to Erase and Write the EEPROM . . . . . . . 109 8.3.3 The CONFIG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.4 The EEPROM Memory of the AVR Microcontrollers . . . . . . . . . . . . 111 8.4.1 The Registers of the Interface with the EEPROM Memory . . 111 8.4.2 Software Routines to Read and Write EEPROM . . . . . . . . . . 112
XIV Contents
9 HC11 Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.1 In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.2 Description of the Hardware Module . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.3 Assembling and Testing the Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.4 Description of the Software Components . . . . . . . . . . . . . . . . . . . . . . . 119 9.5 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10 AVR Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.1 In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.2 The Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.3 Testing the Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.4 The Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.5 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11 8051 Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.1 In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.2 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.3 The Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.3.1 Installing the Cross-Assembler . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.3.2 Writing and Testing Simple 8051 Programs . . . . . . . . . . . . . . 149
11.3.3 Loading and Executing Programs in the External Ram
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.4 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12 Digital Voltmeter with RS232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.1 In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.2 The Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.3 The Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.4 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
13 Simple RS485 Network with Microcontrollers . . . . . . . . . . . . . . . . . . . . . |
163 |
||
13.1 |
In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
163 |
|
13.2 |
The Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
163 |
|
13.2.1 |
The RS232-to-RS485 Converter . . . . . . . . . . . . . . . . . . . . . . . . |
164 |
|
13.2.2 |
The Digital Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
165 |
|
13.2.3 |
The Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
166 |
|
13.2.4 |
Using the AVR Development Board to Emulate Thel SLD |
||
and SLA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
166 |
||
13.3 |
The Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
167 |
|
13.3.1 |
Description of the Communication Protocol . . . . . . . . . . . . . . |
167 |
|
13.3.2 |
The Software for the SLD Module . . . . . . . . . . . . . . . . . . . . . . |
169 |
|
13.3.3 |
The Software for the MASTER Device . . . . . . . . . . . . . . . . . . |
171 |
|
13.4 |
Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
172 |
|
Contents |
XV |
|
14 PI Temperature Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
173 |
|
14.1 |
In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
173 |
14.2 |
Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
173 |
14.3 |
Hardware Implementation of a Microcontroller-Based Temperature |
|
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
177 |
|
14.4 |
Software Implementation of a PI Temperature Controller . . . . . . . . . |
179 |
15 Fuzzy Logic Temperature Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.1 In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.2 The Principles of Fuzzy Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.3 A Microcontroller Implementation of a Fuzzy Controller . . . . . . . . . 189
16 Remote Relay Controller over Telephone Lines . . . . . . . . . . . . . . . . . . . . |
193 |
|
16.1 |
In this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
193 |
16.2 |
Description of the Hardware Solution . . . . . . . . . . . . . . . . . . . . . . . . . . |
193 |
16.3 |
Description of the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
197 |
A.1 |
Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
203 |
Appendix |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
202 |
A.2 |
Description of the Registers of 68HC11F1 . . . . . . . . . . . . . . . . . . . . . . |
213 |
A.3 |
HC11 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
215 |
A.4 |
An Example of Expanded Structure with HC11 . . . . . . . . . . . . . . . . . |
219 |
A.5 |
Using HC11 in Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
221 |
A.6 |
The Registers of AT90S8535 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
224 |
A.7 |
AVR Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
225 |
A.8 |
AT90S8515 Operating with External RAM . . . . . . . . . . . . . . . . . . . . . |
228 |
A.9 |
In-system Programming the AVR AT90S8535 . . . . . . . . . . . . . . . . . . |
229 |
A.10 |
The Special Function Registers of 8051 . . . . . . . . . . . . . . . . . . . . . . . . |
232 |
A.11 |
8051 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
233 |
A.12 |
An Example of 8051 Operating with External Bus . . . . . . . . . . . . . . . |
237 |
A.13 |
Programming the Internal Memory of 8051 . . . . . . . . . . . . . . . . . . . . . |
238 |
A.14 |
SPI Seven-Segment Display Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
240 |
A.15 |
Description of the Software Utility ASMEDIT . . . . . . . . . . . . . . . . . . |
243 |
B.1 |
Contents of the Accompanying CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
245 |
B.2 |
Recommended Readings and Web References . . . . . . . . . . . . . . . . . . . |
247 |
Index . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
249 |
1
Resources of Microcontrollers
1.1 In this Chapter
This chapter is a presentation of the main subsystems of microcontrollers, seen as resources, organized according to one of the fundamental architectures: Von Neumann and Harvard. It also contains a description of the internal CPU registers, the general structure of a peripheral interface, and an overview of the interrupt system.
1.2 Microcontroller Architectures
A microcontroller is a structure that integrates in a single chip a microprocessor, a certain amount of memory, and a number of peripheral interfaces.
The Central Processing Unit (CPU) is connected to the other subsystems of the microcontroller by means of the address and data buses. Depending on how the CPU accesses the program memory, there are two possible architectures for microcontrollers, called Von Neumann, and Harvard.
Figure 1.1 shows the structure of a computer with Von Neumann architecture, where all the resources, including program memory, data memory, and I/O registers, are connected to the CPU by means of a unique address and data bus.
Address bus |
||||||||||||||||||||||||
Data bus |
||||||||||||||||||||||||
PROGRAM |
CPU |
I/O |
DATA |
|||||||||||||||||||||
MEMORY |
||||||||||||||||||||||||
MEMORY |
INTERFACES |
|||||||||||||||||||||||
Interrupt |
||||||||||||||||||||||||
logic |
||||||||||||||||||||||||
Fig. 1.1. Block diagram of Von Neumann architecture
21 Resources of Microcontrollers
A typical microcontroller having Von Neumann architecture is 68HC11 from Motorola. In HC11, all resources are identified by unique addresses in the same address space, and can be accessed using the same instructions. For example, in case of the instruction:
LDAA |
<address> |
;load accumulator a from <address> |
the operand indicated by the label
can be any of the microcontroller’s resources, from I/O ports, to ROM constants. This way of accessing resources allows the existence of complex instructions like this:ASL |
35,x |
;arithmetic shift left the |
memory |
;location with the address |
;obtained by adding 35 to the ;index register X.
Therefore, the Von Neumann microcontrollers tend to have a large instruction set, including some really complex instructions. This is the reason why computers having the Von Neumann architecture are often called CISC, or Complex Instruction Set Computers.
The main disadvantage of this architecture is that the more complex the instruction, the longer it takes to fetch, decode, execute it, and store the result. The instruction in the above example takes six machine cycles to execute, while the instruction for integer divide, IDIV, needs no less than 41 machine cycles to complete.
The Harvard architecture was created to increase the overall speed of computers in the early years, when very slow magnetic core memory was used to store the program. It includes an additional, separate bus to access the program memory (refer to Fig. 1.2).
The presence of the second bus makes the following things possible:
•While an instruction is executed, the next instruction can be fetched from the program memory. This technique is called pipelining and brings a significant increase of computer speed.
•The program memory can be organized in words of different size from, and usually larger than, the data memory. Wider instructions mean a greater data flow to the CPU, and therefore the overall speed is higher.
Address bus |
|||||||||||||||||||||
Address bus |
Data bus |
||||||||||||||||||||
PROGRAM |
I/O |
DATA |
|||||||||||||||||||
CPU |
INTERFACES |
||||||||||||||||||||
MEMORY |
MEMORY |
||||||||||||||||||||
Data bus |
Interrupt |
||||||||||||||||||||
logic |
|||||||||||||||||||||
Fig. 1.2. Block diagram of Harvard architecture
1.3 The Memory Map |
3 |
Such architecture, along with reducing and optimizing the instruction set, mean that most instructions execute in a single machine cycle. Since the Harvard architecture is often accompanied by the reduction of the size and complexity of the instruction set, computers with this architecture are also called Reduced Instruction Set Computers (RISC). For example, some PIC microcontrollers have an instruction set of only 35 instructions, compared to more than 100 for HC11. The speed increase is even higher.
The separate bus for the program memory makes the access of the program to constants (such as tables, strings, etc.) located in ROM more complicated and more restrictive. For example, some PIC microcontrollers have the program memory organized in 14-bit wide words, which makes locating and accessing a constant presented as a byte possible only by embedding the constant in a special instruction. For this purpose, the instruction “RETLW k” (Return from subprogram with constant k in register W) has been provided.
The AVR microcontrollers have the program memory organized into 16-bit words, which makes the task of accessing constants in program memory easier, because each 16-bit word can store two 8-bit constants. A special instruction LPM (Load from Program Memory) allows access to ROM constants.
1.3 The Memory Map
From the programmer’s point of view, a microcontroller is a set of resources. Each resource is identified by one or more addresses in an address space. For example, the 68HC11E9 microcontroller has its internal RAM memory organized as 512 locations, having addresses in the range $0000–$01FF, the ROM memory occupies the addresses in the range $D000–$FFFF (12288 locations), and the I/O register block takes the address form $1000–$103F (64 locations).
The memory map is a graphic representation of how the resources are associated with addresses (see Fig. 1.3 for an example of a memory map).
Obviously, not all addresses are related to existing resources – in some cases it is possible to add external memory or I/O devices, to which we must allocate distinct addresses in the address space.
Normally, the memory map is determined by the hardware structure formed by the microcontroller and the external devices (if any), and cannot be dynamically modified during the execution of a program.
However, there are situations when, by writing into some special configuration registers, the user can disable resources (such as the internal ROM memory, or the EEPROM memory) or can relocate resources in a different area of the address space. But even in these cases, the access to the configuration registers is restricted, and the modification becomes effective after the next RESET.
Figures 1.3 and 1.4 show the memory maps for a microcontroller with Von Neumann architecture, MC68HC11E9, operating in single-chip mode, and for a RISC microcontroller, the AVR AT90S8535.
4 |
1 Resources of Microcontrollers |
|||
$0000 |
Internal RAM |
|||
$01FF |
||||
$1000 |
Register block |
|||
$103F |
||||
$B600 |
||||
$B7FF |
Internal EEPROM |
|||
$D000 |
Internal ROM |
|||
$FFFF |
||||
Fig. 1.3. Memory map for 68HC11E9 operating in single-chip mode
CPU |
$0000 |
||||
register |
$0020 |
||||
I/O |
|||||
register |
|||||
$0060 |
|||||
Internal |
|||||
$0000 |
RAM |
$025F |
|||
Program |
$0000 |
||||
memory |
Not used |
||||
EEPROM |
|||||
$0FFF |
$FFFF |
$01FF |
|||
Fig. 1.4. Memory map for AT90S8515 operating in single-chip mode
Note, for the AVR microcontroller, the presence of three different address spaces, one for data memory and I/O registers, and two more for the program memory and the EEPROM.
The 8051 microcontrollers are considered to belong to the Harvard architecture, but they are CISC, and do not allow pipelining; therefore they look more like Von Neumann computers with the capability to access program memory, and data memory as different pages. The two distinct memory pages are accessed through the same physical bus, at different moments time in. Fig. 1.5 shows the memory map for an 8051 MCU operating in single-chip mode. There are two address spaces here too, one for the program memory and the other for data memory and special function registers.
CPU |
$0000 |
|||
registers |
||||
Bit |
$0020 |
|||
memory |
||||
Internal |
$0030 |
|||
$0000 |
RAM |
|||
Internal |
$0080 |
|||
program |
||||
memory |
SFRs |
|||
$1FFF |
$00FF |
Fig. 1.5. Memory map for 8051 operating in single-chip mode