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212 Appendices
Stack pointer
A register used to address the stack. The stack pointer points to the top of the stack. Depending on the implementation, the top of the stack can be defined as the first empty location in the stack, or as the most recently pushed data.
See also: Stack
Start bit
In asynchronous serial communication, before the actual data transmission begins, the transmission line is pulled to the polarity opposite to the polarity of the idle line, for a duration of a bit time. This technique is destined to provide a means to synchronize the receiver.
See also: Asynchronous communication, Stop bit
Stop bit
In asynchronous serial communication, after the transmission of the data bits and any parity bit, the polarity of the transmission line is returned to the polarity of the idle line for the duration of a bit time.
See also: Asynchronous communication, Start bit
Synchronous communication
Communication technique that requires a common clock signal for the transmitter and receiver(s) in order to coordinate (synchronize) their activity.
See also: Asynchronous communication, SCI, SPI
UART
Acronym for Universal Asynchronous Receiver Transmitter. Interface circuit for asynchronous communication.
See also: Asynchronous communication, SCI
Von Neumann
Computer architecture characterized by common address and data buses for program memory and data memory.
See also: Architecture, Harvard
A.2 Description of the Registers of 68HC11F1
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
PORTA |
PA7 |
PA6 |
PA5 |
PA4 |
PA3 |
PA2 |
PA1 |
PA0 |
DDRA |
DDA7 |
DDA6 |
DDA5 |
DDA4 |
DDA3 |
DDA2 |
DDA1 |
DDA0 |
PORTG |
PG7 |
PG6 |
PG5 |
PG4 |
PG3 |
PG2 |
PG1 |
PG0 |
DDRG |
DDG7 |
DDG6 |
DDG5 |
DDG4 |
DDG3 |
DDG2 |
DDG1 |
DDG0 |
PORTB |
PB7 |
PB6 |
PB5 |
PB4 |
PB3 |
PB2 |
PB1 |
PO |
PORTF |
PF7 |
PF6 |
PF5 |
PF4 |
PF3 |
PF2 |
PF1 |
PO |
PORTC |
PC7 |
PC6 |
PC5 |
PC4 |
PC3 |
PC2 |
PC1 |
PC0 |
DDRC |
DDC7 |
DDC6 |
DDC5 |
DDC4 |
DDC3 |
DDC2 |
DDC1 |
DDC0 |
PORTD |
0 |
0 |
PD5 |
PD4 |
PD3 |
PD2 |
PD1 |
PO |
DDRD |
0 |
0 |
DDD5 |
DDD4 |
DDD3 |
DDD2 |
DDD1 |
DDD0 |
PORTE |
PE7 |
PE6 |
PE5 |
PE4 |
PE3 |
PE2 |
PE1 |
PO |
CFORC |
FOC1 |
FOC2 |
FOC3 |
FOC4 |
FOC5 |
0 |
0 |
0 |
OC1M |
OC1M7 |
OC1M6 |
OC1M5 |
OC1M4 |
OC1M3 |
0 |
0 |
0 |
OC1D |
OC1D7 |
OC1D6 |
OC1D5 |
OC1D4 |
OC1D3 |
0 |
0 |
0 |
TCNTH |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TCNTL |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TIC1H |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TIC1L |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TIC2H |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TIC2L |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TIC3H |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TIC3L |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TOC1H |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TOC1L |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TOC2H |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TOC2L |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TOC3H |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TOC3L |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TOC4H |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TOC4L |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TI4/O5H |
Bit 15 |
14 |
13 |
12 |
11 |
10 |
9 |
Bit 8 |
TI4/O5L |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
TCTL1 |
OM2 |
OL2 |
OM3 |
OL3 |
OM4 |
OL4 |
OM5 |
OM5 |
TCTL2 |
EDG4B |
EDG4A |
EDG1B |
EDG1A |
EDG2B |
EDG2A |
EDG3B |
EDG3A |
TMSK1 |
OC1I |
OC2I |
OC3I |
OC4I |
I4/O5 |
IC1I |
IC2I |
IC3I |
TFLG1 |
OC1F |
OC2F |
OC3F |
OC4F |
I4/O5F |
IC1F |
IC2F |
IC3F |
TMSK2 |
TOI |
RTII |
PAOVI |
PAII |
0 |
0 |
PR1 |
PR0 |
TFLG2 |
TOF |
RTIF |
PAOVF |
PAIF |
0 |
0 |
0 |
0 |
PACTL |
0 |
PAEN |
PAMOD |
PEDGE |
0 |
I4/O5 |
RTR1 |
RTR0 |
PACNT |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit0 |
SPCH |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit0 |
SPSR |
SPIE |
SPE |
DWOM |
MSTR |
CPOL |
CPHA |
SPR1 |
CPO |
SPDR |
SPIF |
WCOL |
0 |
MODF |
0 |
0 |
0 |
Bit0 |
BAUD |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit0 |
214 |
Appendices |
||||||||
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
||
SCCR1 |
TCLR |
0 |
SCP1 |
SCP0 |
RCKB |
SCR2 |
SCR1 |
SCR0 |
|
SCCR2 |
R8 |
T8 |
0 |
M |
WAKE |
0 |
0 |
0 |
|
SCSR |
TIE |
TCIE |
RIE |
ILIE |
TE |
RE |
RWU |
SBK |
|
SCDR |
TDRE |
TC |
RDRF |
IDLE |
OR |
NF |
FE |
0 |
|
ADCTL |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit0 |
|
ADR1 |
CCF |
0 |
SCAN |
MULT |
CD |
CC |
CB |
CA |
|
ADR2 |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit0 |
|
ADR3 |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit0 |
|
ADR4 |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit0 |
|
BROT |
0 |
0 |
0 |
PTCON |
BPRT3 |
BPRT2 |
BPRT1 |
BPRT0 |
|
OPT2 |
GWOM |
CWOM |
CLK4X |
0 |
0 |
0 |
0 |
0 |
|
OPTION |
ADPU |
CSEL |
IRQE |
DLY |
CME |
FCME |
CR1 |
CR0 |
|
COPRST |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit O |
|
PPROG |
ODD |
EVEN |
0 |
BYTE |
ROW |
ERASE |
EELAT |
EEPGM |
|
HPRIO |
RBOOT |
SMOD |
MDA |
IRV |
PSEL3 |
PSEL2 |
PSEL1 |
PSEL0 |
|
INIT |
RAM3 |
RAM2 |
RAM1 |
RAM0 |
REG3 |
REG2 |
REG1 |
REG0 |
|
TEST1 |
TILOP |
0 |
OCCR |
CBYP |
DISR |
FCM |
FCOP |
0 |
|
CONFIG |
EE3‘ |
EE2 |
EE1 |
EEO |
1 |
NOCOP |
1 |
EEON |
|
CSSTRH |
IO1SA |
IO1SB |
IO2SA |
IO2SB |
GSTHA |
GSTHB |
PSTHA |
PSTHB |
|
CSCTL |
IO1EN |
IO1PL |
IO2EN |
IO2PL |
GCSPR |
PCSEN |
PSIZA |
PSIZB |
|
CSGADR GA15 |
GA14 |
GA13 |
GA12 |
GA11 |
GA10 |
0 |
0 |
||
CSGSIZ |
IO1AV |
IO2AV |
0 |
GNPOL |
GAVLD |
GSIZA |
GSIZB |
GSIZC |
|
Note
The register block of 68HC11F1 is located by default in the address range $1000– $105F. The whole block can be relocated by writing the control bits [REG3–REG0] in the INIT register. Consult the data sheets for details on the registers of other HC11 family members.
A.3 HC11 Instruction Set
Mnemonic |
Operation |
Description |
Flags |
ABA |
Add Accumulators |
A + B → A |
H,N,Z,V,C |
ABX |
Add B to X |
IX + (00 : B) → IX |
|
ABY |
Add B to Y |
IY + (00 : B) → IY |
|
ADCA (opr) |
Add with Carry to A |
A + M + C → A |
H,N,Z,V,C |
ADCB (opr) |
Add with Carry to B |
B + M + C → B |
H,N,Z,V,C |
ADDA (opr) |
Add Memory to A |
A + M → A |
H,N,Z,V,C |
ADDB (opr) |
Add Memory toB |
B + M → B |
H,N,Z,V,C |
ADDD (opr) |
Add 16-Bit to D |
D + (M : M + 1) → D |
N,Z,V,C |
ANDA (opr) |
AND A with Memory |
A ∩ M → A |
N,Z,V |
ANDB (opr) |
AND B with Memory |
B ∩ M → B |
N,Z,V |
ASL (opr) |
Arithmetic Shift Left |
C ← b7 ← b6 . . . b0 ← 0 |
N,Z,V,C |
ASLA |
Arithmetic Shift Left A |
C ← b7 ← b6 . . . b0 ← 0 |
N,Z,V,C |
ASLB |
Arithmetic Shift Left B |
C ← b7 ← b6 . . . b0 ← 0 |
N,Z,V,C |
ASLD |
Arithmetic Shift Left D |
C ← b15 ← b14 . . . b0 ← 0 |
N,Z,V,C |
ASR |
Arithmetic Shift Right |
b7 → b7 → . . . b0 → C |
N,Z,V,C |
ASRA |
Arithmetic Shift Right A |
b7 → b7 → b6 → . . . |
N,Z,V,C |
→ b0 → C |
|||
ASRB |
Arithmetic Shift Right B |
b7 → b7 → b6 → . . . |
N,Z,V,C |
→ b0 → C |
BCC (rel) |
Branch if Carry Clear |
BCLR (opr) |
Clear Bit(s) |
(msk) |
|
BCS (rel) |
Branch if Carry Set |
BEQ (rel) |
Branch if = Zero |
BGE (rel) |
Branch if >= Zero |
BGT (rel) |
Branch if > Zero |
BHI (rel) |
Branch if Higher |
BHS (rel) |
Branch if Higher or Same |
BITA (opr) |
Bit(s)Test A with Memory |
BITB (opr) |
Bit(s)Test B with Memory |
BLE (rel) |
Branch if <= Zero |
BLO (rel) |
Branch if Lower |
BLS (rel) |
Branch if Lower or Same |
BLT (rel) |
Branch if < Zero |
BMI (rel) |
Branch if Minus |
BNE (rel) |
Branch if not = Zero |
BPL (rel) |
Branch if Plus |
BRA (rel) |
Branch Always |
BRCLR(opr) |
Branch if Bit(s) Clear |
(msk) (rel) |
|
BRN (rel) |
Branch Never |
BRSET(opr) |
Branch if Bit(s) Set |
(msk) (rel) |
|
BSET (opr) |
Set Bit(s) |
(msk) |
Branch if C = 0 |
|
M ∩ (mm) → M |
N,Z,V |
Branch if C = 1 |
|
Branch if Z = 1 |
|
Branch if N V = 0 |
|
Branch if Z (N V) = 0 |
|
Branch if C Z = 0 |
|
Branch if C = 0 |
|
A ∩ M |
N,Z,V |
B ∩ M |
N,Z,V |
Branch if Z (N V) = 1 |
|
Branch if C = 1 |
|
Branch if C Z = 1 |
|
Branch if N V = 1 |
|
Branch if N = 1 |
|
Branch if Z = 0 |
|
Branch if N = 0 |
|
Branch if 1 = 1 |
|
Branch if M ∩ mm = 0 |
|
Branch if 1 = 0 |
|
Branch if (M) ∩ mm = 1 |
|
M mm → M |
N,Z,V |
216 |
Appendices |
|||
Mnemonic |
Operation |
Description |
Flags |
|
BSR (rel) |
Branch to Subroutine |
Branch if V = 0 |
||
BVC (rel) |
Branch if Overflow Clear |
|||
BVS (rel) |
Branch if Overflow Set |
Branch if V = 1 |
||
CBA |
Compare A to B |
A − B |
N,Z,V,C |
|
CLC |
Clear Carry Bit |
0 → C |
C |
|
CLI |
Clear Interrupt Mask |
0 → I |
I |
|
CLR (opr) |
Clear Memory Byte |
0 → M |
N,Z,V,C |
|
CLRA |
Clear Accumulator A |
0 → A |
N,Z,V,C |
|
CLRB |
Clear Accumulator B |
0 → B |
N,Z,V,C |
|
CLV |
Clear Overflow Flag |
0 → V |
V |
|
CMPA (opr) |
Compare A to Memory |
A − M |
N,Z,V,C |
|
CMPB (opr) |
Compare B to Memory |
B − M |
N,Z,V,C |
|
COM (opr) |
One’s Complement Memory Byte |
$FF − M → M |
N,Z,V,C |
|
COMA |
Ones Complement A |
$FF − A → A |
N,Z,V,C |
|
COMB |
Ones Complement B |
$FF − B → B |
N,Z,V,C |
|
CPD (opr) |
Compare D to Memory 16-Bit |
D − (M : M + 1) |
N,Z,V,C |
|
CPX (opr) |
Compare X to Memory 16-Bit |
IX − (M : M + 1) |
N,Z,V,C |
|
CPY (opr) |
Compare Y to Memory 16-Bit |
IY − (M : M + 1) |
N,Z,V,C |
|
DAA |
Decimal Adjust A |
Adjust Sum to BCD |
N,Z,V,C |
|
DEC (opr) |
Decrement Memory Byte |
M − 1 → M |
N,Z,V |
|
DECA |
Decrement Accumulator A |
A − 1 → A |
N,Z,V |
|
DECB |
Decrement Accumulator B |
B − 1 → B |
N,Z,V |
|
DES |
Decrement Stack Pointer |
SP − 1 → SP |
||
DEX |
Decrement Index Register X |
IX − 1 → IX |
Z |
|
DEY |
Decrement Index Register Y |
IY − 1 → IY |
Z |
|
EORA (opr) |
Exclusive OR A with Memory |
A M → A |
N,Z,V |
|
EORB (opr) |
Exclusive OR B with Memory |
B M → B |
N,Z,V |
|
FDIV |
Fractional Divide 16 by 16 |
D / IX → IX; r → D |
Z,V,C |
|
IDIV |
Integer Divide 16 by 16 |
D / IX → IX; r → D |
Z,V,C |
|
INC (opr) |
Increment Memory Byte |
M + 1 → M |
N,Z,V |
|
INCA |
Increment Accumulator A |
A + 1 → A |
N,Z,V |
|
INCB |
Increment Accumulator B |
B + 1 → B |
N,Z,V |
|
INS |
Increment Stack Pointer |
SP + 1 → SP |
||
INX |
Increment Index Register X |
IX + 1 → X |
Z |
|
INY |
Increment Index Register Y |
IY+1 → Y |
X |
|
JMP(opr) |
Unconditional Jump |
|||
JSR(opr) |
Jump to subroutine |
M → A |
||
LDAA(opr) |
Load Accumulator A |
N,Z,V |
||
LDAB(opr) |
Load Accumulator B |
M → B |
N,Z,V |
|
LDD(opr) |
Load Double Accumulator D |
M → A, M + 1 → B |
N,Z,V |
|
LDS(opr) |
Load Stack Pointer |
(M : M + 1) → SP |
N,Z,V |
|
LDX(opr) |
Load Index Register X |
(M : M + 1) → IX |
N,Z,V |
|
LDY(opr) |
Load Index Register Y |
(M : M + 1) → IY |
N,Z,V |
|
LSL(opr) |
Logical shift left |
C ← b7 ← b6 . . . b0 ← 0 |
N,Z,V,C |
|
LSLA |
Logical shit left A |
C ← b7 ← b6 . . . b0 ← 0 |
N,Z,V,C |
|
LSLB |
Logical shift left B |
C ← b7 ← b6 . . . b0 ← 0 |
N,Z,V,C |
|
LSLD |
Logical shift left Double |
C ← b15 ← . . . ← b0 ← 0 |
N,Z,V,C |
|