ВУЗ: Не указан
Категория: Не указан
Дисциплина: Не указана
Добавлен: 14.06.2025
Просмотров: 3121
Скачиваний: 0
A.5 Using HC11 in Bootstrap Mode |
223 |
DLOOP DEX
BNE DLOOP
CLR PPROG
RTS
END
Remember that the EEPROM cells that form the CONFIG register are doubled by a RAM-type register for read operations, which is loaded only once, at RESET. Any new value written to the CONFIG register becomes visible after the next RESET.
Important note. Do not clear the bit NOCOP in the CONFIG register unless you really want to enable the watchdog. Also note that some HC11 versions have a special bit in CONFIG, called NOSEC. Clearing this bit enables a security feature, which prevents the MCU from entering the bootstrap operating mode. You may not be able to erase the CONFIG register again.
A.6 The Registers of AT90S8535
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit0 |
|
SREG |
I |
T |
H |
S |
V |
N |
Z |
C |
SPH |
– |
– |
– |
– |
– |
SP10 |
SP9 |
SP8 |
SPL |
SP7 |
SP6 |
SP5 |
SP4 |
SP3 |
SP2 |
SP1 |
SP0 |
GIMSK |
INT1 |
INT0 |
||||||
GIFR |
INTF1 |
INTF0 |
||||||
TIMSK |
OCIE2 |
TOIE2 |
TICIE1 |
OCIE1A |
OCIE1B |
TOIE1 |
TOIEO |
|
TIFR |
OCF2 |
TOV2 |
ICF1 |
OCF1A |
OCF1B |
TOV1 |
TOV0 |
|
MCUCR |
SE |
SM1 |
SM0 |
ISC11 |
ISC10 |
ISC01 |
ISC00 |
|
MCUCSR |
EXTRF |
PORF |
||||||
TCCR0 |
CS02 |
CS01 |
CS00 |
|||||
TCNT0 |
Timer/Counter0 (8 Bits) |
|||||||
TCCR1A |
COM1A1 |
COM1A0 |
COM1B1 |
COM1B0 |
PWM11 |
PWM10 |
||
TCCR1B |
ICNC1 |
ICES1 |
CTC1 |
CS12 |
CS11 |
CS10 |
||
TCNT1H |
Timer/Counter1 – Counter Register High Byte |
|||||||
TCNT1L |
Timer/Counter1 – Counter Register Low Byte |
|||||||
OCR1AH |
Timer/Counter1 – Output Compare Register A High Byte |
|||||||
OCR1AL |
Timer/Counter1 – Output Compare Register A Low Byte |
|||||||
OCR1BH |
Timer/Counter1 – Output Compare Register B High Byte |
|||||||
OCR1BL |
Timer/Counter1 – Output Compare Register B Low Byte |
|||||||
ICR1H |
Timer/Counter1 – Input Capture Register High Byte |
|||||||
ICR1L |
Timer/Counter1 – Input Capture Register Low Byte |
|||||||
TCCR2 |
PWM2 |
COM21 |
COM20 |
WGM21 |
CS22 |
CS21 |
CS20 |
|
TCNT2 |
Timer/Counter2 (8 Bits) |
|||||||
OCR2 |
Timer/Counter2 Output Compare Register |
|||||||
ASSR |
– |
– |
– |
– |
AS2 |
TCN2UB |
OCR2UB |
TCR2UB |
WDTCR |
– |
– |
– |
WDTOE |
WDE |
WDP2 |
WDP1 |
WDP0 |
UCSRC |
URSEL |
UMSEL |
UPM1 |
UPM0 |
USBS |
UCSZ1 |
UCSZ0 |
UCPOL |
EEARH |
– |
– |
– |
– |
– |
– |
– |
EEAR8 |
EEARL |
EEPROM Address Register Low Byte |
|||||||
EEDR |
EEPROM Data Register |
|||||||
EECR |
– |
– |
– |
– |
EERIE |
EEMWE |
EEWE |
EERE |
PORTA |
PORTA7 |
PORTA6 |
PORTA5 |
PORTA4 |
PORTA3 |
PORTA2 |
PORTA1 |
PORTA0 |
DDRA |
DDA7 |
DDA6 |
DDA5 |
DDA4 |
DDA3 |
DDA2 |
DDA1 |
DDA0 |
PINA |
PINA7 |
PINA6 |
PINA5 |
PINA4 |
PINA3 |
PINA2 |
PINA1 |
PINA0 |
PORTB |
PORTB7 |
PORTB6 |
PORTB5 |
PORTB4 |
PORTB3 |
PORTB2 |
PORTB1 |
PORTB0 |
DDRB |
DDB7 |
DDB6 |
DDB5 |
DDB4 |
DDB3 |
DDB2 |
DDB1 |
DDB0 |
PINB |
PINB7 |
PINB6 |
PINB5 |
PINB4 |
PINB3 |
PINB2 |
PINB1 |
PINB0 |
PORTC |
PORTC7 |
PORTC6 |
PORTC5 |
PORTC4 |
PORTC3 |
PORTC2 |
PORTC1 |
PORTC0 |
DDRC |
DDC7 |
DDC6 |
DDC5 |
DDC4 |
DDC3 |
DDC2 |
DDC1 |
DDC0 |
PINC |
PINC7 |
PINC6 |
PINC5 |
PINC4 |
PINC3 |
PINC2 |
PINC1 |
PINC0 |
PORTD |
PORTD7 |
PORTD6 |
PORTD5 |
PORTD4 |
PORTD3 |
PORTD2 |
PORTD1 |
PORTD0 |
DDRD |
DDD7 |
DDD6 |
DDD5 |
DDD4 |
DDD3 |
DDD2 |
DDD1 |
DDD0 |
PIND |
PIND7 |
PIND6 |
PIND5 |
PIND4 |
PIND3 |
PIND2 |
PIND1 |
PIND0 |
SPDR |
SPI Data Register |
|||||||
SPSR |
SPIF |
WCOL |
– |
– |
– |
– |
– |
SPI2X |
SPCR |
SPIE |
SPE |
DORD |
MSTR |
CPOL |
CPHA |
SPR1 |
SPR0 |
UDR |
USART I/O Data Register |
|||||||
USR |
RXC |
TXC |
UDRE |
FE |
OR |
|||
UCR |
RXCIE |
TXCIE |
UDRIE |
RXEN |
TXEN |
CHR9 |
RXB8 |
TXB8 |
UBRR |
USART Baud Rate Register Low Byte |
|||||||
ACSR |
ACD |
ACO |
ACI |
ACIE |
ACIC |
ACIS1 |
AC IS0 |
|
ADMUX |
MUX2 |
MUX1 |
MUX0 |
|||||
ADCSR |
ADEN |
ADSC |
ADFR |
ADIF |
ADIE |
ADPS2 |
ADPS1 |
ADPS0 |
ADCH |
ADC Data Register High Byte |
|||||||
ADCL |
ADC Data Register Low Byte |
|||||||
A.7 AVR Instruction Set
Arithmetic and Logic Instructions
Mnemonic |
Description |
Operation |
Flags |
|
ADD |
Rd, Rr |
Add two Registers |
Rd ← Rd + Rr |
Z,C,N,V,H |
ADC |
Rd, Rr |
Add with Carry two Registers |
Rd ←Rd + Rr + C |
Z,C,N,V,H |
ADIW |
Rdl.K |
Add Immediate to Word |
Rdh:Rdl ← Rdh:Rdl + K |
Z,C,N,V,S |
SUB |
Rd, Rr |
Subtract two Registers |
Rd ← Rd − Rr |
Z,C,N,V,H |
SUBI |
Rd, K |
Subtract Constant from Register |
Rd ← Rd − K |
Z,C,N,V,H |
SBC |
Rd, Rr |
Subtract with Carry two Registers |
Rd ← Rd − Rr − C |
Z,C,N,V,H |
SBCI |
Rd, K |
Subtract with Carry Constant from Reg. |
Rd ← Rd − K − C |
Z,C,N,V,H |
SBIW |
Rdl.K |
Subtract Immediate from Word |
Rdh:Rdl←Rdh:Rdl −,K |
Z,C,N,V,S |
AND |
Rd, Rr |
Logical AND Registers |
Rd ← Rd · Rr |
Z,N,V |
ANDI |
Rd,K |
Logical AND Register and Constant |
Rd ← Rd · K |
Z,N,V |
OR |
Rd, Rr |
Logical OR Registers |
Rd ← Rd v Rr |
Z,N,V |
ORI |
Rd, K |
Logical OR Register and Constant |
Rd ← Rd v K |
Z,N,V |
EOR |
Rd, Rr |
Exclusive OR Reqisters |
Rd ← Rd 0 Rr |
Z,N,V |
COM |
Rd |
One’s Complement |
Rd ← 0xFF − Rd |
Z,C,N,V |
NEG |
Rd |
Two’s Complement |
Rd ← 0x00 − Rd |
Z,C,N,V,H |
SBR |
Rd,K |
Set Bit(s) in Register |
Rd ← Rd v K |
Z,N,V |
CBR |
Rd,K |
Clear Bit(s) in Register |
Rd ← Rd (0Xff − K) |
Z,N,V |
INC |
Rd |
Increment |
Rd ← Rd + 1 |
Z,N,V |
DEC |
Rd |
Decrement |
Rd ← Rd − 1 |
Z,N,V |
TST |
Rd |
Test for Zero or Minus |
Rd ← Rd · Rd |
Z,N,V |
CLR |
Rd |
Clear Register |
Rd ← Rd 0 Rd |
Z,N,V |
SER |
Rd |
Set Register |
Rd ← 0xFF |
None |
Branch Instructions
Mnemonic |
Description |
Operation |
Flags |
|
RJMP |
k |
Relative Jump |
PC ← PC + k + 1 |
None |
IJMP |
Indirect Jump to (Z) |
PC ← Z |
None |
|
RCALL |
k |
Relative Subroutine Call |
PC ← PC + k + 1 |
None |
ICALL |
Indirect Call to (Z) |
PC ← Z |
None |
|
RET |
Subroutine Return |
PC ← STACK |
None |
|
RETI |
Interrupt Return |
PC ← STACK |
I |
|
CPSE |
Rd,Rr |
Compare, Skip if Equal |
If(Rd = r)PC ← PC + 2 or 3 |
None |
CP |
Rd,Rr |
Compare |
Rd − Rr |
Z,N,V,C,H |
CPC |
Rd,Rr |
Compare with Carry |
Rd − Rr − C |
Z,N,V,C,H |
CPI |
Rd,K |
Compare Register with Immediate |
Rd − K |
Z,N,V,C,H |
SBRC |
Rr, b |
Skip if Bit in Reqister Cleared |
If(Rr(b) = 0)PC ← PC + 2 or 3 |
None |
SBRS |
Rr, b |
Skip if Bit in Registeris Set |
if(Rr(b) = 1)PC ← PC + 2 or 3 |
None |
SBIC |
P,b |
Skip if Bit in I/O Register Cleared |
if(P(b) = 0)PC ← PC + 2 or 3 |
None |
SBIS |
P,b |
Skip if Bit in I/O Register is Set |
if (P(b) = 1)PC ← PC + 2 or 3 |
None |
BRBS |
s,k |
Branch if Status Flag Set |
if (SREG(s) = 1) then PC ← PC + k + 1 |
None |
BRBC |
s,k |
Branch if Status Flag Cleared |
if (SREG(s) = 0) then PC ← PC + k + 1 |
None |
BREQ |
K |
Branch if Equal |
if (Z = 1) then PC ← PC + k + 1 |
None |
BRNE |
K |
Branch if Not Equal |
if (Z = 0) then PC ← PC + k + 1 |
None |
BRCS |
K |
Branch if Carry Set |
if (C = 1) then PC ← PC + k + 1 |
None |
BRCC |
K |
Branch if Carry Cleared |
if (C = 0) then PC ← PC + k + 1 |
None |
BRSH |
K |
Branch if Same or Higher |
if (C = 0) then PC ← PC + k + 1 |
None |
BRLO |
K |
Branch if Lower |
if (C = 1) then PC ← PC + k + 1 |
None |
BRMI |
K |
Branch if Minus |
if (N = 1) then PC ← PC + k + 1 |
None |
BRPL |
K |
Branch if Plus |
if (N = 0) then PC ← PC + k + 1 |
None |
226 Appendices
Mnemonic |
Description |
Operation |
Flags |
BRGE |
K |
Branch if Greater or Equal, Signed |
BRLT |
K |
Branch if Less Than Zero, Signed |
BRHS |
K |
Branch if Half Carry Flag Set |
BRHC |
K |
Branch if Half Carry Flag Cleared |
BRTS |
K |
Branch if T Flag Set |
BRTC |
K |
Branch if T Flag Cleared |
BRVS |
K |
Branch if Overflow Flag is Set |
BRVC |
k |
Branch if Overflow Flag is Cleared |
BRIE |
k |
Branch if Interrupt Enabled |
BRID |
k |
Branch if Interrupt Disabled |
if (N 0 V = 0) then PC ← PC + k + 1 |
None |
if (N 0 V = 1) then PC ← PC + k + 1 |
None |
if (H = 1) then PC ← PC + k + 1 |
None |
if (H = 0) then PC ← PC + k + 1 |
None |
if (T = 1) then PC ← PC + k + 1 |
None |
if (T = 0) then PC ← PC + k + 1 |
None |
if (V = 1) then PC ← PC + k + 1 |
None |
if (V = 0) then PC ← PC + k + 1 |
None |
if (I = 1) then PC ← PC + k + 1 |
None |
if (l = 0) then PC ← PC + k + 1 |
None |
Data Transfer Instructions
Mnemonic |
Description |
Operation |
Flags |
|
MOV |
Rd, Rr |
Move Between Registers |
Rd ← Rr |
None |
LDI |
Rd, K |
Load Immediate |
Rd ← K |
None |
LD |
Rd, X |
Load Indirect |
Rd ← (X) |
None |
LD |
Rd, X + |
Load Indirect and Post-Inc. |
Rd ← (X), X ← X + 1 |
None |
LD |
Rd,−X |
Load Indirect and Pre-Dec. |
X← X − 1, Rd ← (X) |
None |
LD |
Rd, Y |
Load Indirect |
Rd ← (Y) |
None |
LD |
Rd, Y + |
Load Indirect and Post-Inc. |
Rd ← (Y), Y← Y + 1 |
None |
LD |
Rd,−Y |
Load Indirect and Pre-Dec. |
Y←Y − 1,Rd ← (Y) |
None |
LDD |
Rd,Y + q |
Load Indirect with Displacement |
Rd ← (Y + q) |
None |
LD |
Rd, Z |
Load Indirect |
Rd ← (Z) |
None |
LD |
Rd, Z + |
Load Indirect and Post-Inc. |
Rd ← (Z),Z ← Z + 1 |
None |
LD |
Rd,−Z |
Load Indirect and Pre-Dec. |
Z ← Z − 1,Rd ← (Z) |
None |
LDD |
Rd, Z + q |
Load Indirect with Displacement |
Rd ← (Z + q) |
None |
LDS |
Rd, k |
Load Direct from SRAM |
Rd ← (k) |
None |
ST |
X,Rr |
Store indirect |
(X) ← Rr |
None |
ST |
X + , Rr |
Store indirect and Post-Inc |
(X) ← Rr, X ← X + 1 |
None |
ST |
−X, Rr |
Store indirect and Pre-Dec |
X ← X − 1,(X) ← Rr |
None |
ST |
Y, Rr |
Store indirect |
(Y) ← Rr |
None |
ST |
Y + , Rr |
Store indirect and Post-Inc |
(Y) ← Rr, Y ← Y + 1 |
None |
ST |
−Y, Rr |
Store indirect and Pre-Dec |
Y ← Y − 1,(Y) ← Rr |
None |
STD |
Y + q,Rr |
Store indirect with Displacement |
(Y + q) ← Rr |
None |
ST |
Z, Rr |
Store indirect |
(Z) ← Rr |
None |
ST |
Z + , Rr |
Store indirect and Post-Inc |
(Z) ← Rr, Z ← Z + 1 |
None |
ST |
−Z, Rr |
Store indirect and Pre-Dec |
Z ← Z − 1,(Z) ← Rr |
None |
STD |
Z + q,Rr |
Store indirect with Displacement |
(Z + q)← Rr |
None |
STS |
k, Rr |
Store Direct to SRAM |
(k) ← Rr |
None |
LPM |
Load Program Memory |
R0 ← (Z) |
None |
|
IN |
Rd, P |
In Port |
RdˆP |
None |
OUT |
P,Rr |
Out Port |
P ← Rr |
None |
PUSH |
Rr |
Push Register on Stack |
STACK ← Rr |
None |
POP |
Rd |
Pop Register from Stack |
Rd ← STACK |
None |
A.7 AVR Instruction Set |
227 |
||||
Bit and Bit-test Instructions |
|||||
Mnemonic |
Description |
Operation |
Flags |
||
SBI |
P,b |
Set Bit in I/O Register |
I/O(P,b) ← 1 |
None |
|
CBI |
P,b |
Clear Bit in I/O Register |
I/O(P,b) ← 0 |
None |
|
LSL |
Rd |
Logical Shift Left |
Rd(n + 1) ← Rd(n),Rd(0) ← 0 |
Z,C,N,V |
|
LSR |
Rd |
Logical Shift Right |
Rd(n) ← Rd(n + 1), Rd(7) ← 0 |
Z,C,N,V |
|
ROL |
Rd |
Rotate Left Through Carry |
Rd(0) ← C,Rd(n + 1) ← Rd(n),C ← Rd(7) |
Z,C,N,V |
|
ROR |
Rd |
Rotate Right Through Carry |
Rd(7) ← C,Rd(n) ← Rd(n + 1),C ← Rd(0) |
Z,C,N,V |
|
ASR |
Rd |
Arithmetic Shift Right |
Rd(n) ← Rd(n + 1),n = 0..6 |
Z,C,N,V |
|
SWAP |
Rd |
Swap Nibbles |
Rd(3-0) ← Rd(7–4),Rd(7-4) ← Rd(3–0) |
None |
|
BSET |
s |
Flag Set |
SREG(s) ← 1 |
SREG(s) |
|
BCLR |
s |
Flaq Clear |
SREG(s) ← 0 |
SREG(s) |
|
BST |
Rr, b |
Bit Store from Register to T |
T ← Rr(b) |
T |
|
BLD |
Rd, b |
Bit load from T to Register |
Rd(b) ← T |
None |
|
SEC |
Set Carry |
C ← 1 |
C |
||
CLC |
Clear Carry |
C ← O |
C |
||
SEN |
Set Negative Flag |
N ← 1 |
N |
||
CLN |
Clear Negative Flag |
N ← O |
N |
||
SEZ |
Set Zero Flag |
Z ← 1 |
Z |
||
CLZ |
Clear Zero Flag |
Z ← O |
Z |
||
SEI |
Global Interrupt Enable |
l ← 1 |
I |
||
CLI |
Global Interrupt Disable |
l ← 0 |
I |
||
SES |
Set Signed Test Flag |
S ← 1 |
S |
||
CLS |
Clear Signed Test Flag |
S ← O |
S |
||
SEV |
Set V |
V ← 1 |
V |
||
CLV |
Clear V |
V ← O |
V |
||
SET |
Set T in SREG |
T ← 1 |
T |
||
CLT |
Clear T in SREG |
T ← O |
T |
||
SEH |
Set Half Carry Flag in SREG |
H ← 1 |
H |
||
CLH |
Clear Half Carry Flag in SREG |
H ← O |
H |
||
Special Instructions |
|||||
Mnemonic |
Description |
Operation |
Flags |
||
NOP |
No Operation |
None |
|||
SLEEP |
Sleep |
None |
|||
WDR |
Watchdog Reset |
None |
|||