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for these reasons digital to analog converters (DACs) are not often found as an integral function in most MCU families.

We have already seen that a rather crude way of providing this mapping is to vary the mark:space ratio of a pulse train of constant repetitive duration, as shown in Fig. 13.9 on page 380. Here a small digital number gives a skinny pulse, which when smoothed out by a low-pass filter (which gives the average or d.c. value) translates to a low voltage. Conversely, a large digital number leads to a correspondingly large mark:space ratio, which in turn after smoothing yields a higher voltage.

PWM conversion can be very accurate and is simple to implement. However, extensive filtering is required to remove harmonics of the pulse rate and this makes the conversion slow to respond to changes in the digital input. Normally PWM is used to control heavy loads, such as motors or heaters, where the inertia of these devices inherently provides the smoothing action. Furthermore, the pulsed nature of the signal is ideally suited to power control, activating thyristor firing circuits.

Many commercial DAC devices are available which can be controlled via standard digital I/O ports. Two examples were given in Figs. 12.4 and 12.6 on pages 310 and 314 where the MCU transferred digital data in series. Here we will look at an example where parallel data transfer is used.

The majority of proprietary devices are based on an R-2R ladder network, such as that shown in Fig. 14.12(a). Voltage appearing at any bit switch node emerges at the output node in an attenuated form. As our analysis will show, each move to the left attenuates this voltage bn by 50%, which is the binary weighting relationship:

N+1

V = bn × 2i

i=0

for an N-bit word.

In Fig. 14.6(b) at mode A looking to the left we see a resistance of R (2R//2R) and the voltage is attenuated by two. As we move to the right the process is repeated with each voltage divided by two. Thus, at node B the voltage b0/2 is further divided by two and the next digital node voltage is divided by two giving VB= b0/4 + b1/2. As the network is symmetrical the resistance looking right at any mode is also 2R. This means that as seen from any digital switch, the total resistance is 2R + 2R//2R = 3R. This is important as the characteristics of a transistor switch, such as resistance, are dependent on current and keeping this the same reduces error.

For clarity our analysis has been for three bits. This can be extended by simply moving the leftmost terminating resistor over and inserting the requisite number of sections. This does not a ect the resistance as seen left of the mode, and therefore does not change the conditions of the

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rightmost sections. An inspection of our analysis shows that nowhere does the absolute value of resistance appear. In fact the accuracy of the analysis depends only on the R:2R ratio. While it is relatively easy to fabricate accurate ratioed resistors on a silicon die, this is certainly not the case for absolute values. For this reason R:2R networks are the standard technique used for most integrated circuit DACs.

The Maxim MAX506 is an example of a commercial D/A converter (DAC). This 20-pin footprint device contains four separate DACs sharing a common external Vref. Digital data is presented to the D7:0 pins and one of four latch registers selected with the A1:0 address inputs. Once this is done, the datum byte is loaded into the selected register n and appears at the corresponding output VOUTn.

This output analog voltage ranges from zero (Analog GrouND) for a

digital input of 00h through to Vref for a digital input of FFh.

Where VSS is connected to ground then Vref can be anything between

0 V and VDD (+5 V). However, VSS can be as low as −5 V and in this case Vref can be anywhere in the range ±5 V. If Vref is negative for dual supplies then the output voltage will also be negative. In either case, e ectively

the output can be treated as the product D × Vref where D is the digital input byte scaled to the range 0 – 1 (00 – FFh).

The MAX505 24-pin variant allows for separate reference voltages to be used for each of the four DAC channels. In addition, the MAX505’s DAC latches are isolated from the converter ladder circuits by a further layer of latches all clocked at the same time with a LDAC (Load DAC) control signal. This double bu ering permits the programmer to update all four DACs simultaneously after their individual latches have been set up.

As an example, consider that a MAX506 quad DAC has its Address selected via RA1:0 and RA2 drives the WR input to latch in the addressed data from Port B. A software routine to generate a continuous staircase sawtooth waveform from DACD would look something like:

where we are assuming that Port B and Port A[2:0] have been set up as outputs.

A typical DAC staircase output waveform is shown in the oscillogram in Fig. 14.13. Here a 12 MHz crystal clocked PIC is shown which, with a

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1 V/div

TIME BASE 0.1 ms/div

Fig. 14.13 Generating a continuous sawtooth using a MAX506 DAC.

loop cycle count of 6 cycles, gives a sawtooth duration of (256 × 6)/3 ≈ 0.5 ms at 2 µs per step.

Examples

Example 14.1

Augment the interrupt-driven ISR of Program 14.2 to implement a 16deep bu er array of data to allow a limited mismatch between acquisition and reading rates.

Solution

One approach is shown in Fig. 14.14. A block of file registers is set aside by the programmer together with any other variables used by the programmer with a cblock directive of the form:

cblock

ARRAY:16, OVERFLOW:1, BUF_EMPTY:1, ... ; etc. endc

and the File Select Register used as a bu er pointer to the next empty location in the array of samples.

In acquiring data the foreground ISR of Program 14.6 simply pushes the datum from the ADRES into the location pointed to by the FSR using

420 The Quintessential PIC Microcontroller

ARRAY

FSR

datum

Interrupt

Fig. 14.14 Bu ered data acquisition.

the indirect address mode and then increments this pointer ready for the next event.

The problem with this approach is that if the background program does not pull data out of the bu er quickly enough, decrementing the FSR, the bu er will overflow. As a consequence, if there are variables stored above ARRAY+15 then they will be overwritten. In order to avoid this problem, on overflow no more data should be saved and the state of the OVERFLOW file register set to non zero to show the background software that data has been lost.

Based on this ISR, a background routine to fetch data from the bu er would be something like this:

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Program 14.6 Bu ered interrupt-driven data acquisition.

;**********************************************************

;* FUNCTION: ISR to read the A/D converter at EOC and put *

;**********************************************************

;First save context

; ************************************************************

; ************************************************************

It is essential to avoid any alteration to the FSR during a background bu er fetch, so GIE is zeroed before and enabled after the process to disable interrupts. If the bu er pointer is at the bottom of the array then no update is carried out and the file register EMPTY is left at zero to show that the bu er was empty. Otherwise the datum pointed to is copied to the Working register; the bu er pointer is decremented and EMPTY is set to non zero.