Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

42END IF;

43END IF;

44END IF;

45END PROCESS;

46END rtl;

47-------------------------------------------------

Simulation results are presented in figure 9.14. The input sequence is din ¼ {start ¼ 1, din ¼ 0111001, parity ¼ 0, stop ¼ 1}. As can be seen in the upper graph, no error was detected in this case, because the parity and stop bits are correct. Hence, after count reaches 9, the data is made available, that is, data ¼ 0111001, from data(0) to data(6), which corresponds to the decimal 78, and the data_valid bit is

Figure 9.14

Simulation results of serial data receivers.

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asserted. Notice that the output remains so indefinitely, unless a new input train is received.

The only di¤erence in the lower graph is that a start bit appears immediately after the stop bit. As can be seen, the count variable starts then to count and the whole process is repeated.

9.7Parallel-to-Serial Converter

A parallel-to-serial converter is a typical application of shift registers. It consists of sending out a block of data serially. The need for such converters arises, for example, in ASIC chips when there are not enough pins available to output all data bits simultaneously.

A diagram of a parallel-to-serial converter is presented in figure 9.15. d(7:0) is the data vector to be sent out, while dout is the actual output. There are also two other inputs: clk and load. When load is asserted, d is synchronously stored in the shift register reg. While load stays high, the MSB, d(7), remains available at the output. Once load is returned to ‘0’, the subsequent bits are presented at the output at each positive edge of clk. After all eight bits have been sent out, the output remains low until the next transmission.

1 -------------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -------------------------------------------------

5ENTITY serial_converter IS

6PORT ( d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

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Figure 9.16

Simulation results of parallel-to-serial converter.

11 ARCHITECTURE serial_converter OF serial_converter IS

12SIGNAL reg: STD_LOGIC_VECTOR (7 DOWNTO 0);

13BEGIN

14PROCESS (clk)

15BEGIN

16IF (clk'EVENT AND clk='1') THEN

17IF (load='1') THEN reg <= d;

18ELSE reg <= reg(6 DOWNTO 0) & '0';

19END IF;

20END IF;

21END PROCESS;

22dout <= reg(7);

23END serial_converter;

24-------------------------------------------------

Simulation results from the circuit synthesized with the code above are shown in figure 9.16. d ¼ ‘‘11011011’’ (decimal 219) was chosen. As can be seen, d(7) ¼ ‘1’ is presented at the output at the first rising edge of clk after load has been asserted, staying there while load remains high (to illustrate this fact, load was kept high during two clock cycles). The other bits follow as soon as load returns to ‘0’. Notice that after all bits have been transmitted, the output stays low.

9.8 Playing with a Seven-Segment Display

We want to design a little game with an SSD (seven-segment display). The top-level diagram of the circuit is shown in figure 9.17. It contains two inputs, clk and stop, and one output, dout(6:0), which feeds the SSD. Assume that fclk ¼ 1 kHz.

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Our circuit should cause a continuous clockwise movement of the SSD segments. Also, in order to make the circulatory movement more realistic, we want to momentarily overlap neighboring segments. Consequently, the sequence should be a ! ab ! b ! bc ! c ! cd ! d ! de ! e ! ef ! f ! fa ! a, with the combined states (ab, bc, etc.) lasting only a few milliseconds. If stop is asserted, then the circuit should return to state a and remain so until stop is turned low again.

From chapter 8, it is clear that this is a circuit for which the FSM approach is appropriate. The states diagram is presented in figure 9.18. We want the system to remain in states a, b, c, etc. for time1 ¼ 80 ms, and in the combined states, ab, bc, etc., for time2 ¼ 30 ms. Therefore, a counter counting up to 80 (the clock period is 1 ms) or up to 30 can be employed to determine when to move to the next state.

A VHDL solution is shown below. Notice that it is a straight implementation of the FSM template seen in section 8.2. In lines 11–12, time1 and time2 were declared as two constants. Small values (4 and 2, respectively) were here used in order for the simulation results to fit well in one plot, but 80 and 30, respectively, were used in the actual physical implementation. A signal called flip was used to switch from time1 to time2, and vice-versa. Notice that the corresponding decimals are marked beside each value of dout, so they can be easily verified in the simulation results.

1 --------------------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 --------------------------------------------------------

5ENTITY ssd_game2 IS

6 PORT ( clk, stop: IN BIT;

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10 ARCHITECTURE fsm OF ssd_game2 IS

11CONSTANT time1: INTEGER := 4; -- actual value is 80

12CONSTANT time2: INTEGER := 2; -- actual value is 30

13TYPE states IS (a, ab, b, bc, c, cd, d, de, e, ef, f, fa);

14SIGNAL present_state, next_state: STATES;

15SIGNAL count: INTEGER RANGE 0 TO 5;

16SIGNAL flip: BIT;

17BEGIN

18------- Lower section of FSM (Sec. 8.2): ------------

19PROCESS (clk, stop)

20BEGIN

21IF (stop='1') THEN

22present_state <= a;

23ELSIF (clk'EVENT AND clk='1') THEN

24IF ((flip='1' AND count=time1) OR

25(flip='0' AND count=time2)) THEN

26count <= 0;

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27present_state <= next_state;

28ELSE count <= count + 1;

29END IF;

30END IF;

31END PROCESS;

32------- Upper section of FSM (Sec. 8.2): ------------

33PROCESS (present_state)

34BEGIN

35CASE present_state IS

36WHEN a =>

37dout <= "1000000"; -- Decimal 64

38flip<='1';

39next_state <= ab;

40WHEN ab =>

41dout <= "1100000"; -- Decimal 96

42flip<='0';

43next_state <= b;

44WHEN b =>

45dout <= "0100000"; -- Decimal 32

46flip<='1';

47next_state <= bc;

48WHEN bc =>

49dout <= "0110000"; -- Decimal 48

50flip<='0';

51next_state <= c;

52WHEN c =>

53dout <= "0010000"; -- Decimal 16

54flip<='1';

55next_state <= cd;

56WHEN cd =>

57dout <= "0011000"; -- Decimal 24

58flip<='0';

59next_state <= d;

60WHEN d =>

61dout <= "0001000"; -- Decimal 8

62flip<='1';

63next_state <= de;

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64WHEN de =>

65dout <= "0001100"; -- Decimal 12

66flip<='0';

67next_state <= e;

68WHEN e =>

69dout <= "0000100"; -- Decimal 4

70flip<='1';

71next_state <= ef;

72WHEN ef =>

73dout <= "0000110"; -- Decimal 6

74flip<='0';

75next_state <= f;

76WHEN f =>

77dout <= "0000010"; -- Decimal 2

78flip<='1';

79next_state <= fa;

80WHEN fa =>

81dout <= "1000010"; -- Decimal 66

82flip<='0';

83next_state <= a;

84END CASE;

85END PROCESS;

86END fsm;

87--------------------------------------------------------

Simulation results are presented in figure 9.19. As can be seen, the system stays in the single states, a, b, etc., for four clock cycles (time1 ¼ 4 here) and in the combined states, ab, bc, etc., for two clock cycles (time2 ¼ 2). Observe also that the decimals detected by the simulator match the decimals listed in the VHDL code.

Figure 9.19

Simulation results of little SSD game of figure 9.17.

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9.9Signal Generators

Say that, from a clock signal (clk), we want to obtain the waveform shown in figure 9.20. In this kind of problem, we can use either the FSM approach or a conventional approach. Both kinds of solutions are illustrated below.

FSM Approach

The signal of figure 9.20 can be modeled as an 8-state FSM. Using a counter from 0 to 7, we can establish that wave ¼ ‘0’ (1st pulse) when count ¼ 0, wave ¼ ‘1’ (2nd pulse) when count ¼ 1, and so on, thus creating the signal shown in the figure. This implementation requires a total of four flip-flops: three to store count (three bits), plus one to store wave (one bit). Recall from chapter 8, sections 8.2–8.3, that the output of a FSM will only be registered if design style #2 is employed, which is necessary here, because glitches are not acceptable in a signal generator.

The corresponding VHDL code, using dsign style #2 (section 8.3), is shown below. Simulation results appear in figure 9.21. Checking the report file created by the synthesis tool, we verify that a total of four flip-flops were indeed inferred from this code.

1 -----------------------------------------------------

2LIBRARY ieee;

3USE ieee.std_logic_1164.all;

clk

wave

1 period

Figure 9.20

Signal generator problem.

Figure 9.21

Simulation results of signal generator (FSM approach).

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4 -----------------------------------------------------

5ENTITY signal_gen IS

6PORT (clk: IN STD_LOGIC;

13SIGNAL present_state, next_state: STATES;

14SIGNAL temp: STD_LOGIC;

15BEGIN

16

17--- Lower section of FSM (Sec. 8.3): ---

18PROCESS (clk)

19BEGIN

20IF (clk'EVENT AND clk='1') THEN

21present_state <= next_state;

22wave <= temp;

23END IF;

24END PROCESS;

25

26--- Upper section of FSM (Sec. 8.3): ---

27PROCESS (present_state)

28BEGIN

29CASE present_state IS

30WHEN zero => temp<='0'; next_state <= one;

31WHEN one => temp<='1'; next_state <= two;

32WHEN two => temp<='0'; next_state <= three;

33WHEN three => temp<='1'; next_state <= four;

34WHEN four => temp<='1'; next_state <= five;

35WHEN five => temp<='1'; next_state <= six;

36WHEN six => temp<='0'; next_state <= seven;

37WHEN seven => temp<='0'; next_state <= zero;

38END CASE;

39END PROCESS;

40END fsm;

41 -----------------------------------------------------

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