Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

10err : OUT STD_LOGIC);

11END divider;

12 --------------------------------------------------

13 ARCHITECTURE rtl OF divider IS

14BEGIN

15PROCESS (a, b)

16VARIABLE temp1: INTEGER RANGE 0 TO 15;

17VARIABLE temp2: INTEGER RANGE 0 TO 15;

18BEGIN

19----- Error and initialization: -------

20temp1 := a;

21temp2 := b;

22IF (b=0) THEN err <= '1';

23ELSE err <= '0';

24END IF;

25----- y: ------------------------------

26FOR i IN n DOWNTO 0 LOOP

27IF(temp1 >= temp2 * 2**i) THEN

28y(i) <= '1';

29temp1 := temp1 - temp2 * 2**I;

30ELSE y(i) <= '0';

31END IF;

32END LOOP;

33----- Remainder: ----------------------

34rest <= temp1;

35END PROCESS;

36END rtl;

37 --------------------------------------------------

9.5Vending-Machine Controller

In this example, we will design a controller for a vending machine, which sells candy bars for twenty-five cents. As seen in chapter 8, this is the type of design where the FSM (finite state machine) model is helpful.

The inputs and outputs of the controller are shown in figure 9.11. The input signals nickel_in, dime_in, and quarter_in indicate that a corresponding coin has been deposited. Two additional inputs, clk (clock) and rst (reset), are also necessary. The

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Figure 9.11

Vending-machine controller (top-level and states diagrams). The signals are. ni ¼ nickel_in, di ¼ dime_in, qi ¼ quarter_in, no ¼ nickel_out, do ¼ dime_out, and co ¼ candy_out.

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controller responds with three outputs: candy_out, to dispense a candy bar, plus nickel_out and dime_out, asserted when change is due.

Figure 9.11 also shows the states of the corresponding FSM. The numbers inside the circles represent the total amount deposited by the customer (only nickels, dimes, and quarters are accepted). State 0 is the idle state. From it, if a nickel is deposited, the machine moves to state 5; if a dime, to state 10; or if a quarter, to state 25. Similar situations are repeated for all states, up to state 20. If state 25 is reached, then a candy bar is dispensed, with no change. However, if state 40 is reached, for example, then a nickel is delivered, passing therefore the system to state 35, from which a dime is delivered and a candy bar dispensed. The three states marked with double circles are those from which a candy bar is delivered and the machine returns to state 0.

This problem will be divided into two parts: in the first, the fundamental aspects related to the design of the vending machine controller (figure 9.11) are treated; in the second, additional (and indispensable) features are added. The first part is studied in this section, while the second is proposed as a problem (problem 9.3). The introduction of such additional features is necessary for safety reasons; since we are dealing with money, we must assure that none of the parts (machine or customer) will be hurt in the transaction.

A VHDL code, treating only the basic features of the problem depicted in figure 9.11, is presented below. We have assumed that the additional features proposed in problem 9.3 will indeed be implemented, in which case glitches are acceptable in the first part of the solution. Therefore, design style #1 (section 8.2) can be employed.

The enumerated type state (line 12) contains a list of all states shown in the FSM diagram of figure 9.11. There are ten states, so four bits are necessary to encode them (so four flip-flops will be inferred). Recall that the compiler encodes such states in the order that they are listed, so st0 ¼ ‘‘0000’’ (decimal 0), st5 ¼ ‘‘0001’’ (decimal 1), . . . , st45 ¼ ‘‘1001’’ (decimal 9). Therefore, in the simulations, such numbers are shown instead of the state names.

1 ------------------------------------------------------

2LIBRARY ieee;

3USE ieee.std_logic_1164.all;

4 ------------------------------------------------------

5ENTITY vending_machine IS

6PORT ( clk, rst: IN STD_LOGIC;

7nickel_in, dime_in, quarter_in: IN BOOLEAN;

9END vending_machine;

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10------------------------------------------------------

11ARCHITECTURE fsm OF vending_machine IS

12TYPE state IS (st0, st5, st10, st15, st20, st25,

13st30, st35, st40, st45);

14SIGNAL present_state, next_state: STATE;

15BEGIN

16---- Lower section of the FSM (Sec. 8.2): ---------

17PROCESS (rst, clk)

18BEGIN

19IF (rst='1') THEN

20present_state <= st0;

21ELSIF (clk'EVENT AND clk='1') THEN

22present_state <= next_state;

23END IF;

24END PROCESS;

25---- Upper section of the FSM (Sec. 8.2): ---------

26PROCESS (present_state, nickel_in, dime_in, quarter_in)

27BEGIN

28CASE present_state IS

29WHEN st0 =>

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99END CASE;

100END PROCESS;

102END fsm;

103------------------------------------------------------

Simulation results are presented in figure 9.12. As can be seen, three nickels and one quarter were deposited. Notice that, at the first positive clock edge after the first nickel was deposited, the FSM moves from state st0 (decimal 0) to st5 (decimal 1);

Figure 9.12

Simulation results from the vending-machine controller.

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after de second nickel, to state st10 (decimal 2); after de third, to state st15 (decimal 3); and, after de quarter has been deposited, to state st40 (decimal 8). After that, a nickel is returned to the customer (nickel_out ¼ ‘1’), causing the FSM to move to state st35 (decimal 7), at which a dime is delivered (dime_out ¼ ‘1’) and a candy bar is dispensed (candy_out ¼ ‘1’). The system returns then to its idle state (st0).

As mentioned above, additional features (like handshake) are necessary to increase the security of the transactions. Please refer to problem 9.3 for a continuation of this design.

9.6 Serial Data Receiver

The diagram of a serial data receiver is shown in figure 9.13. It contains a serial data input, din, and a parallel data output, data(6:0). A clock signal is also needed at the input. Two supervision signals are generated by the circuit: err (error) and data_valid.

The input train consists of ten bits. The first bit is a start bit, which, when high, must cause the circuit to start receiving data. The next seven are the actual data bits. The ninth bit is a parity bit, whose status must be ‘0’ if the number of ones in data is even, or ‘1’ otherwise. Finally, the tenth is a stop bit, which must be high if the transmission is correct. An error is detected when either the parity does not check or the stop bit is not a ‘1’. When reception is concluded and if no error has been detected, then the data stored in the internal registers (reg) is transferred to data(6:0) and the data_valid output is asserted.

A VHDL code for this circuit is presented below. A few variables were used: count, to determine the number of bits received; reg, which stores the data; and temp, to compute the error. Notice in line 37 that reg(0) ¼ din was used instead of reg(0) ¼ ‘0’, because we want the time slot immediately after the stop bit to be considered as possibly containing a start bit for the next input train.

data

start parity stop

Serial data receiver.

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1 ---------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------------

5ENTITY receiver IS

6PORT ( din, clk, rst: IN BIT;

11 ARCHITECTURE rtl OF receiver IS

12BEGIN

13PROCESS (rst, clk)

14VARIABLE count: INTEGER RANGE 0 TO 10;

15VARIABLE reg: BIT_VECTOR (10 DOWNTO 0);

16VARIABLE temp : BIT;

17BEGIN

18IF (rst='1') THEN

19count:=0;

20reg := (reg'RANGE => '0');

21temp := '0';

22err <= '0';

23data_valid <= '0';

24ELSIF (clk'EVENT AND clk='1') THEN

25IF (reg(0)='0' AND din='1') THEN

26reg(0) := '1';

27ELSIF (reg(0)='1') THEN

28count := count + 1;

29IF (count < 10) THEN

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