Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

Figure 9.22

Simulation results of signal generator (conventional approach).

Conventional Approach

A conventional design, with the IF statement, is shown next. Notice that count and wave are both assigned at the transition of another signal (clk). Therefore, according to what you saw in section 7.5, both will be stored (that is, four flip-flops will be inferred, three for count and one for wave). Simulation results are shown in figure 9.22.

1 ---------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------

5 ENTITY signal_gen1 IS

6 PORT (clk: IN BIT;

7 wave: OUT BIT);

8 END signal_gen1;

9 ---------------------------------------

10 ARCHITECTURE arch1 OF signal_gen1 IS

11BEGIN

12PROCESS

13VARIABLE count: INTEGER RANGE 0 TO 7;

14BEGIN

15WAIT UNTIL (clk'EVENT AND clk='1');

16CASE count IS

17WHEN 0 => wave <= '0';

18WHEN 1 => wave <= '1';

19WHEN 2 => wave <= '0';

20WHEN 3 => wave <= '1';

21WHEN 4 => wave <= '1';

22WHEN 5 => wave <= '1';

23WHEN 6 => wave <= '0';

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ROM

word 0

Figure 9.23

ROM diagram.

24WHEN 7 => wave <= '0';

25END CASE;

26count := count + 1;

27END PROCESS;

28END arch1;

29---------------------------------------

9.10 Memory Design

In this section, the design of the following memory circuits is presented:

ROM

RAM with separate in/out data buses

RAM with bidirectional in/out data bus

ROM (Read Only Memory)

Figure 9.23 shows the diagram of a ROM. Since it is a read-only memory, no clock signal or write-enable pin is necessary. As can be seen, the circuit contains a pile of pre-stored words, being the one selected by the address input (addr) presented at the output (data).

In the code shown below, words (line 7) represents the number of words stored in the memory, while bits (line 6) represents the size of each word. To create a ROM, an array of CONSTANT values can be used (lines 15–22). First, a new TYPE, called vector_array, was defined (lines 13–14), which was then used in the declaration of a CONSTANT named memory (line 15). An 8 8 ROM is illustrated in this example, with the following (decimal) values stored in addresses 0 to 7: 0, 2, 4, 8, 16, 32, 64, and 128 (lines 15–22). Line 24 shows an example of call to the memory; the output (data) is equal to the word stored at address addr. When implementing a ROM, no

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registers are inferred, because no signal assignment occurs at the transition of another signal. Logical gates, forming an LUT (lookup table), are used instead.

1 ---------------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------------------

5ENTITY rom IS

8PORT ( addr: IN INTEGER RANGE 0 TO words-1;

13TYPE vector_array IS ARRAY (0 TO words-1) OF

14STD_LOGIC_VECTOR (bits-1 DOWNTO 0);

15CONSTANT memory: vector_array := ( "00000000",

23BEGIN

24data <= memory(addr);

25END rom;

26 ---------------------------------------------------

Simulation results are shown in figure 9.24. As can be seen, the address changes from 0 to 7, then restarts from 0, with the outputs matching the values listed in the code above.

RAM with Separate Input and Output Data Buses

A RAM (Random Access Memory), with separate input and output data buses, is illustrated in figure 9.25. Indeed, this circuit was already discussed in example 6.11, but was repeated here to ease the comparison with the other memory circuits presented in this section.

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Figure 9.24

Simulation results from the 8 8 ROM code shown above.

clk wr_ena

As can be seen in figure 9.25(a), the circuit has a data input bus (data_in), a data output bus (data_out), an address bus (addr), plus clock (clk) and write enable (wr_ena) pins. When wr_enable is asserted, at the next rising edge of clk the vector present at data_in must be stored in the position specified by addr. data_out, on the other hand, must constantly display the data selected by addr.

From the register point-of-view, the circuit can be summarized as in figure 9.25(b). When wr_ena is low, q is connected to the input of the flip-flop, and terminal d is open, so no new data will be written into the memory. However, when wr_ena is turned high, d is connected to the input of the register, so at the next rising edge of clk d will be stored.

A VHDL code that implements the circuit of figure 9.25 is shown below. The chosen capacity was 16 words of length eight bits each. Notice that the code is totally generic. Simulation results are shown in figure 9.26.

1 ---------------------------------------------------

2 LIBRARY ieee;

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Figure 9.26

Simulation results of 16 8 RAM with separate in/out data buses.

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------------------

5ENTITY ram IS

9PORT ( wr_ena, clk: IN STD_LOGIC;

10addr: IN INTEGER RANGE 0 TO words-1;

11data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);

12data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));

13END ram;

14 ---------------------------------------------------

15 ARCHITECTURE ram OF ram IS

16TYPE vector_array IS ARRAY (0 TO words-1) OF

17STD_LOGIC_VECTOR (bits-1 DOWNTO 0);

18SIGNAL memory: vector_array;

19BEGIN

20PROCESS (clk, wr_ena)

21BEGIN

22IF (wr_ena='1') THEN

23IF (clk'EVENT AND clk='1') THEN

24memory(addr) <= data_in;

25END IF;

26END IF;

27END PROCESS;

28data_out <= memory(addr);

29END ram;

30 ---------------------------------------------------

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clk wr_ena

Figure 9.27

RAM with bidirectional in/out data bus.

Figure 9.28

Simulation results of 16 8 RAM with bidirectional in/out data bus.

RAM with Bidirectional In/Out Data Bus

A RAM with bidirectional in/out data bus is illustrated in figure 9.27. The overall structure is similar to that of figure 9.25, except for the fact that now the same bus (bidir) is used to write data into the memory as well to read data from it.

From the register point-of-view, the circuit can be summarized as in figure 9.27(b). When wr_ena is low, the output of the register is connected to its input, so no change on the store data will occur. On the other hand, when wr_ena is asserted, q is connected to d, allowing new data to be stored at the next rising edge of clk.

A VHDL code that implements the circuit of figure 9.27 is shown below. The chosen capacity was 16 words of length eight bits each. Notice that this code is also totally generic. Simulation results are shown in figure 9.28.

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1 -------------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -------------------------------------------------

5ENTITY ram4 IS

9PORT ( clk, wr_ena: IN STD_LOGIC;

10addr: IN INTEGER RANGE 0 TO words-1;

11bidir: INOUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));

12END ram4;

13 -------------------------------------------------

14 ARCHITECTURE ram OF ram4 IS

15TYPE vector_array IS ARRAY (0 TO words-1) OF

16STD_LOGIC_VECTOR (bits-1 DOWNTO 0);

17SIGNAL memory: vector_array;

18BEGIN

19PROCESS (clk, wr_ena)

20BEGIN

21IF (wr_ena='0') THEN

22bidir <= memory(addr);

23ELSE

24bidir <= (OTHERS => 'Z');

25IF (clk'EVENT AND clk='1') THEN

26memory(addr) <= bidir;

27END IF;

28END IF;

29END PROCESS;

30END ram;

31 -------------------------------------------------

9.11Problems

Problem 9.1: Barrel Shifter

Why can we not replace the ARCHITECTURE of the barrel shifter presented in section 9.1 by that shown below, which is much shorter?

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---------------------------------------------

ARCHITECTURE barrel OF barrel IS

BEGIN

PROCESS (inp, shift)

BEGIN

IF (shift=0) THEN

outp <= inp;

ELSE

FOR i IN 0 TO shift-1 LOOP outp(i) <= '0';

END LOOP;

FOR i IN shift TO inp'HIGH LOOP outp(i) <= inp(i-1);

END LOOP;

END IF;

END PROCESS;

END barrel;

---------------------------------------------

Problem 9.2: Divider

In section 9.4, we studied the design of fixed-point dividers. Two solutions were presented, both using sequential statements (IF and LOOP). Moreover, the codes implemented the second description of the division algorithm presented in that section. You are asked to write a concurrent solution for the division problem (with GENERATE). Additionally, your code should resemble the first description of the division algorithm (figure 9.9). In order to do so, we suggest the creation and use of the following types and signal:

SUBTYPE long IS STD_LOGIC_VECTOR (2n DOWNTO 0);

TYPE vec_array IS ARRAY (n DOWNTO 0) OF long;

SIGNAL a_input, b_input: vec_array;

where n should be declared as a GENERIC parameter.

Problem 9.3: Vending-Machine Controller

Consider the vending-machine controller designed in section 9.5. We want to introduce some sophistications in it.

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