Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

15c <= b;

16dout <= c;

17END IF;

18END PROCESS;

19END shift;

2ENTITY shift IS

3PORT ( din, clk: IN BIT;

7ARCHITECTURE shift OF shift IS

8BEGIN

9PROCESS (clk)

10VARIABLE a, b, c: BIT;

11BEGIN

12IF (clk'EVENT AND clk='1') THEN

13a := din;

14b := a;

15c := b;

16dout <= c;

17END IF;

18END PROCESS;

19END shift;

20 --------------------------------------

Simulation results from solution 1 or 2 are shown in the upper graph of figure 7.12, while the lower graph shows results from solution 3. As expected, dout is four positive clock edges behind din in the former, but only one positive edge behind the input in the latter.

Example 7.9: Shift Register #2

In this example, conventional approaches to the design of shift registers are presented. Figure 7.13 shows a 4-bit shift register, similar to that of example 7.8, except for the presence of a reset input (rst). As before, the output bit (q) should be four positive clock edges behind the input bit (d). Reset should be asynchronous, forcing all flip-

flop outputs to ‘0’ when asserted.

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Figure 7.12

Simulation results of example 7.8 (solutions 1 and 2).

Figure 7.13

Shift register of example 7.9.

Two solutions are presented. One uses a SIGNAL to generate the flip-flops, while the other uses a VARIABLE. The synthesized circuits are the same (that is, four flipflops are inferred from either solution). In solution 1, registers are created because an assignment to a signal is made at the transition of another signal (lines 17–18). In solution 2, the assignment at the transition of another signal is made to a variable (lines 17–18), but since its value does leave the process (that is, it is passed to a port in line 20), it too infers registers.

1 ---- Solution 1: With an internal SIGNAL ---

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 --------------------------------------------

5 ENTITY shiftreg IS

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6PORT ( d, clk, rst: IN STD_LOGIC;

11SIGNAL internal: STD_LOGIC_VECTOR (3 DOWNTO 0);

12BEGIN

13PROCESS (clk, rst)

14BEGIN

15IF (rst='1') THEN

16internal <= (OTHERS => '0');

17ELSIF (clk'EVENT AND clk='1') THEN

18internal <= d & internal(3 DOWNTO 1);

19END IF;

20END PROCESS;

21q <= internal(0);

22END behavior;

23 --------------------------------------------

1 -- Solution 2: With an internal VARIABLE ---

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 --------------------------------------------

5ENTITY shiftreg IS

6PORT ( d, clk, rst: IN STD_LOGIC;

11BEGIN

12PROCESS (clk, rst)

13VARIABLE internal: STD_LOGIC_VECTOR (3 DOWNTO 0);

14BEGIN

15IF (rst='1') THEN

16internal := (OTHERS => '0');

17ELSIF (clk'EVENT AND clk='1') THEN

18internal := d & internal(3 DOWNTO 1);

19END IF;

20q <= internal(0);

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Figure 7.14

Simulation results of example 7.9.

21END PROCESS;

22END behavior;

23--------------------------------------------

Simulation results (from either solution above) are shown in figure 7.14. As can be seen, q is indeed four positive clock edges behind d.

You may now review the usage of SIGNALS and VARIABLES in all examples of chapter 6. Moreover, in chapter 8, a series of design examples will be presented in which the correct understanding of the di¤erences between signals and variables is crucial, or the wrong circuit might be inferred.

7.6Problems

Problem 7.1: VHDL ‘‘Numerical’’ Objects

Given the following VHDL objects:

CONSTANT max : INTEGER := 10;

SIGNAL x: INTEGER RANGE -10 TO 10;

SIGNAL y: BIT_VECTOR (15 DOWNTO 0);

VARIABLE z: BIT;

Determine which among the assignments below are legal (suggestion: review chapter 3).

x <= 5;

x <= y(5); z <= '1'; z := y(5);

WHILE i IN 0 TO max LOOP...

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clk

MUX q

sel

Figure P7.2

FOR i IN 0 TO x LOOP...

G1: FOR i IN 0 TO max GENERATE...

G1: FOR i IN 0 TO x GENERATE...

Problem 7.2: Data Delay

Figure P7.2 shows the diagram of a programmable data delay circuit. The input (d) and output (q) are 4-bit buses. Depending on the value of sel (select), q should be one, two, three, or four clock cycles delayed with respect to d.

(a)Write a VHDL code for this circuit;

(b)How many flip-flops do you expect your solution to contain?

(c)Synthesize your solution and open the report file. Verify whether the actual number of flip-flops matches your prediction.

Problem 7.3: DFF with q and qbar #1

We want to implement the same flip-flop of example 7.4 (figure 7.4). However, we have introduced an auxiliary signal (temp) in our code. You are asked to examine each of the solutions below and determine whether q and qbar will work properly. Briefly explain your answers.

---------------------------------------

ENTITY dff IS

PORT ( d, clk: IN BIT;

q, qbar: BUFFER BIT);

END dff;

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-------- Solution 1 -------------------

ARCHITECTURE arch1 OF dff IS

SIGNAL temp: BIT;

BEGIN

PROCESS (clk)

BEGIN

IF (clk'EVENT AND clk='1') THEN temp <= d;

q <= temp;

qbar <= NOT temp; END IF;

END PROCESS;

END arch1;

-------- Solution 2 -------------------

ARCHITECTURE arch2 OF dff IS

SIGNAL temp: BIT;

BEGIN

PROCESS (clk)

BEGIN

IF (clk'EVENT AND clk='1') THEN temp <= d;

END IF;

q <= temp;

qbar <= NOT temp; END PROCESS;

END arch2;

-------- Solution 3 -------------------

ARCHITECTURE arch3 OF dff IS

SIGNAL temp: BIT;

BEGIN

PROCESS (clk)

BEGIN

IF (clk'EVENT AND clk='1') THEN temp <= d;

END IF;

END PROCESS; q <= temp;

qbar <= NOT temp;

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END arch3;

---------------------------------------

Problem 7.4: DFF with q and qbar #2

This problem is similar to problem 7.3. However, here we have an auxiliary VARIABLE instead of an auxiliary SIGNAL. You are asked to examine each of the solutions below and determine whether q and qbar will work as expected. Briefly explain your answers.

---------------------------------------

ENTITY dff IS

PORT ( d, clk: IN BIT; q: BUFFER BIT; qbar: OUT BIT);

END dff;

-------- Solution 1 -------------------

ARCHITECTURE arch1 OF dff IS

BEGIN

PROCESS (clk)

VARIABLE temp: BIT;

BEGIN

IF (clk'EVENT AND clk='1') THEN temp := d;

q <= temp;

qbar <= NOT temp; END IF;

END PROCESS;

END arch1;

-------- Solution 2 -------------------

ARCHITECTURE arch2 OF dff IS

BEGIN

PROCESS (clk)

VARIABLE temp: BIT;

BEGIN

IF (clk'EVENT AND clk='1') THEN temp := d;

q <= temp; qbar <= NOT q;

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Figure P7.5

END IF;

END PROCESS;

END arch2;

-------- Solution 3 -------------------

ARCHITECTURE arch3 OF dff IS

BEGIN

PROCESS (clk)

VARIABLE temp: BIT;

BEGIN

IF (clk'EVENT AND clk='1') THEN temp := d;

q <= temp; END IF;

END PROCESS; qbar <= NOT q;

END arch3;

---------------------------------------

Problem 7.5: Counter

Consider the 4-bit counter of example 6.2. However, suppose that now it should count from 0 (‘‘0000’’) to 15 (‘‘1111’’).

(a)Write a VHDL code for it, then synthesize and simulate your solution to verify that it works as expected.

(b)Open the report file created by your synthesis tool and confirm that four flipflops were inferred.

(c)Still using the report file, observe whether the circuit looks like that of figure P7.5. Are the equations implemented at the flip-flop inputs similar or equivalent to those shown in figure P7.5? What is the missing equation (input of fourth flip-flop)?

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Problem 7.6: Generic n-by-m Decoder

Let us consider the generic n-by-m decoder presented in example 4.1 (repeated in figure P7.6). The code presented below, though very compact, contains a flaw in the assignment ‘‘x<=(sel=>'0', OTHERS=>'1'’’. The reason is that sel is not a locally stable signal (indeed, it appears in the sensitivity list of the PROCESS). You are asked to correct the code.

---------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

---------------------------------------------

ENTITY decoder IS

PORT ( ena : IN STD_LOGIC;

sel : IN INTEGER RANGE 0 TO 7;

x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END decoder;

---------------------------------------------

ARCHITECTURE not_ok OF decoder IS

BEGIN

PROCESS (ena, sel)

BEGIN

IF (ena='0') THEN

x <= (OTHERS => '1'); ELSE

x <= (sel=>'0', OTHERS => '1'); END IF;

END PROCESS;

END not_ok;

---------------------------------------------

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