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Problem 7.7: DFF with q and qbar #3

Consider the DFF implemented in solution 2 of example 7.6. We are interested in examining the number of registers required in its implementation. We already know that the answer is one. However, as we mentioned in the comments of example 7.6, even though the synthesizer tells us so, the fitter (place & route) might opt for two registers in the final (physical) implementation when q and qbar are connected directly to output pins. This problem deals with this kind of situation.

(a)Compile the code of example 7.6 (solution 2) using Quartus II 3.0 (appendix D). Select a device from the MAX3000A or Cyclone family. In the synthesis reports, verify the number of registers inferred and the equations implemented by the synthesizer (confirming the number of flip-flops). Next, repeat these verifications in the fitter reports (number of registers and equations).

(b)Repeat the procedure above for another device. Select a chip from the FLEX10K family.

(c)Compile now the code of example 7.6 (solution 2) using ISE 6.1 (appendix B). Select a device from the XC9500 or CoolRunner II family. After compilation, make the same verifications described above.

(d)Finally, consider the case when one of the outputs of the flip-flop is not connected directly to a pin. In order to do so, we have introduced a signal called test in the code below. Repeat all topics above for this new code.

1 ----------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ----------------------------------------

5ENTITY dff IS

6PORT ( d, clk, test: IN STD_LOGIC;

7q: BUFFER STD_LOGIC;

12BEGIN

13PROCESS (clk)

14BEGIN

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15IF (clk'EVENT AND clk='1') THEN

16q <= d;

17END IF;

18END PROCESS;

19qbar <= NOT q AND test;

20END one_dff;

21 ----------------------------------------

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8State Machines

Finite state machines (FSM) constitute a special modeling technique for sequential logic circuits. Such a model can be very helpful in the design of certain types of systems, particularly those whose tasks form a well-defined sequence (digital controllers, for example). We start the chapter by reviewing fundamental concepts related to FSM. We then introduce corresponding VHDL coding techniques, followed by complete design examples.

8.1Introduction

Figure 8.1 shows the block diagram of a single-phase state machine. As indicated in the figure, the lower section contains the sequential logic (flip-flops), while the upper section contains the combinational logic.

The combinational (upper) section has two inputs, being one pr_state (present state) and the other the external input proper. It has also two outputs, nx_state (next state) and the external output proper.

The sequential (lower) section has three inputs (clock, reset, and nx_state), and one output (pr_state). Since all flip-flops are in this part of the system, clock and reset must be connected to it.

If the output of the machine depends not only on the present state but also on the current input, then it is called a Mealy machine. Otherwise, if it depends only on the current state, it is called a Moore machine. Examples of both will be shown later.

The separation of the circuit into two sections (figure 8.1) allows the design to be broken into two parts as well. From a VHDL perspective, it is clear that the lower part, being sequential, will require a PROCESS, while the upper part, being combinational, will not. However, recall that sequential code can implement both types of logic, combinational as well as sequential. Hence, if desired, the upper part can also be implemented using a PROCESS.

The signals clock and reset normally appear in the sensitivity list of the lower section’s PROCESS (unless reset is synchronous or not used, or WAIT is used instead of IF). When reset is asserted, pr_state will be set to the system’s initial state. Otherwise, at the proper clock edge the flip-flops will store nx_state, thus transferring it to the lower section’s output (pr_state).

One important aspect related to the FSM approach is that, though any sequential circuit can in principle be modeled as a state machine, this is not always advantageous. The reason is that the code might become longer, more complex, and more error prone than in a conventional approach. This is often the case with simple registered

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Figure 8.1

Mealy (Moore) state machine diagram.

circuits, like counters. As a simple rule of thumb, the FSM approach is advisable in systems whose tasks constitute a well-structured list so all states can be easily enumerated. That is, in a typical state machine implementation, we will encounter, at the beginning of the ARCHITECTURE, a user-defined enumerated data type, containing a list of all possible system states. Digital controllers are good examples of such circuits.

Another important aspect, which was already emphasized at the beginning of chapter 5, is that not all circuits that possess memory are necessarily sequential. A RAM (Random Access Memory) was given as an example. In it, the memory-read operation depends only on the address bits presently applied to the RAM (current input), with the retrieved value having nothing to do with previous memory accesses (previous inputs). In such cases, the FSM approach is not advisable.

8.2 Design Style #1

Several approaches can be conceived to design a FSM. We will describe in detail one style that is well structured and easily applicable. In it, the design of the lower section of the state machine (figure 8.1) is completely separated from that of the upper section. All states of the machine are always explicitly declared using an enumerated data type. After introducing such a design style, we will examine it from a data

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storage perspective, in order to further understand and refine its construction, which will lead to design style #2.

Design of the Lower (Sequential) Section

In figure 8.1, the flip-flops are in the lower section, so clock and reset are connected to it. The other lower section’s input is nx_state (next state), while pr_state (present state) is its only output. Being the circuit of the lower section sequential, a PROCESS is required, in which any of the sequential statements (IF, WAIT, CASE, or LOOP, chapter 6) can be employed.

A typical design template for the lower section is the following:

PROCESS (reset, clock)

BEGIN

IF (reset='1') THEN

pr_state <= state0;

ELSIF (clock'EVENT AND clock='1') THEN pr_state <= nx_state;

END IF;

END PROCESS;

The code shown above is very simple. It consists of an asynchronous reset, which determines the initial state of the system (state0), followed by the synchronous storage of nx_state (at the positive transition of clock), which will produce pr_state at the lower section’s output (figure 8.1). One good thing about this approach is that the design of the lower section is basically standard.

Another advantage of this design style is that the number of registers is minimum. From section 7.5, we know that the number of flip-flops inferred from the code above is simply equal to the number of bits needed to encode all states of the FSM (because the only signal to which a value is assigned at the transition of another signal is pr_state). Therefore, if the default (binary) encoding style (section 8.4) is used, just dlog2ne flip-flops will then be needed, where n is the number of states.

Design of the Upper (Combinational) Section

In figure 8.1, the upper section is fully combinational, so its code does not need to be sequential; concurrent code can be used as well. Yet, in the design template shown below, sequential code was employed, with the CASE statement playing the central role. In this case, recall that rules 1 and 2 of section 6.10 must be observed.

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PROCESS (input, pr_state)

BEGIN

CASE pr_state IS

WHEN state0 =>

IF (input = ...) THEN output <= <value>; nx_state <= state1;

ELSE ...

END IF;

WHEN state1 =>

IF (input = ...) THEN output <= <value>; nx_state <= state2;

ELSE ...

END IF;

WHEN state2 =>

IF (input = ...) THEN output <= <value>; nx_state <= state2;

ELSE ...

END IF;

...

END CASE;

END PROCESS;

As can be seen, this code is also very simple, and does two things: (a) it assigns the output value and (b) it establishes the next state. Notice also that it complies with rules 1 and 2 of section 6.10, relative to the design of combinational circuits using sequential statements, for all input signals are present in the sensitivity list and all input/output combinations are specified. Finally, observe that no signal assignment is made at the transition of another signal, so no flip-flops will be inferred (section 7.5).

State Machine Template for Design Style #1

A complete template is shown below. Notice that, in addition to the two processes presented above, it also contains a user-defined enumerated data type (here called state), which lists all possible states of the machine.

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LIBRARY ieee;

USE ieee.std_logic_1164.all;

-----------------------------------------------------

ENTITY <entity_name> IS

PORT ( input: IN <data_type>; reset, clock: IN STD_LOGIC; output: OUT <data_type>);

END <entity_name>;

-----------------------------------------------------

ARCHITECTURE <arch_name> OF <entity_name> IS

TYPE state IS (state0, state1, state2, state3, ...); SIGNAL pr_state, nx_state: state;

BEGIN

---------- Lower section: ------------------------

PROCESS (reset, clock) BEGIN

IF (reset='1') THEN pr_state <= state0;

ELSIF (clock'EVENT AND clock='1') THEN pr_state <= nx_state;

END IF;

END PROCESS;

output <= <value>; nx_state <= state3;

ELSE ...

END IF;

...

END CASE; END PROCESS; END <arch_name>;

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Figure 8.2

States diagram of example 8.1.

Example 8.1: BCD Counter

A counter is an example of Moore machine, for the output depends only on the stored (present) state. As a simple registered circuit and as a sequencer, it can be easily implemented in either approach: conventional (as we have already done in previous chapters) or FSM type. The problem with the latter is that when the number of states is large it becomes cumbersome to enumerate them all, a problem easily avoided using the LOOP statement in a conventional approach.

The state diagram of a 0-to-9 circular counter is shown in figure 8.2. The states were called zero, one, . . . , nine, each name corresponding to the decimal value of the output.

A VHDL code, directly resembling the design style #1 template, is presented below. An enumerated data type (state) appears in lines 11–12. The design of the lower (clocked) section is presented in lines 16–23, and that of the upper (combinational) section, in lines 25–59. In this example, the number of registers is dlog210e ¼ 4.

Simulation results are shown in figure 8.3. As can be seen, the output (count) grows from 0 to 9, and then restarts from 0 again.

1 -------------------------------------------------

2LIBRARY ieee;

3USE ieee.std_logic_1164.all;

4 -------------------------------------------------

5 ENTITY counter IS

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Figure 8.3

Simulation results of example 8.1.

6PORT ( clk, rst: IN STD_LOGIC;

11TYPE state IS (zero, one, two, three, four,

12five, six, seven, eight, nine);

13SIGNAL pr_state, nx_state: state;

14BEGIN

16PROCESS (rst, clk)

17BEGIN

18IF (rst='1') THEN

19pr_state <= zero;

20ELSIF (clk'EVENT AND clk='1') THEN

21pr_state <= nx_state;

22END IF;

23END PROCESS;

25PROCESS (pr_state)

26BEGIN

27CASE pr_state IS

28WHEN zero =>

29count <= "0000";

30nx_state <= one;

31WHEN one =>

32count <= "0001";

33nx_state <= two;

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34WHEN two =>

35count <= "0010";

36nx_state <= three;

37WHEN three =>

38count <= "0011";

39nx_state <= four;

40WHEN four =>

41count <= "0100";

42nx_state <= five;

43WHEN five =>

44count <= "0101";

45nx_state <= six;

46WHEN six =>

47count <= "0110";

48nx_state <= seven;

49WHEN seven =>

50count <= "0111";

51nx_state <= eight;

52WHEN eight =>

53count <= "1000";

54nx_state <= nine;

55WHEN nine =>

56count <= "1001";

57nx_state <= zero;

58END CASE;

59END PROCESS;

60END state_machine;

61-------------------------------------------------

Example 8.2: Simple FSM #1

Figure 8.4 shows the states diagram of a very simple FSM. The system has two states (stateA and stateB), and must change from one to the other every time d ¼ ‘1’ is received. The desired output is x ¼ a when the machine is in stateA, or x ¼ b when in stateB. The initial (reset) state is stateA.

A VHDL code for this circuit, employing design style #1, is shown below.

1 ----------------------------------------------

2 ENTITY simple_fsm IS

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