Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

rst

clk rst

Figure 8.4

State machine of example 8.1.

3PORT ( a, b, d, clk, rst: IN BIT;

5END simple_fsm;

6 ----------------------------------------------

7 ARCHITECTURE simple_fsm OF simple_fsm IS

8TYPE state IS (stateA, stateB);

9 SIGNAL pr_state, nx_state: state;

10BEGIN

11----- Lower section: ----------------------

12PROCESS (rst, clk)

13BEGIN

14IF (rst='1') THEN

15pr_state <= stateA;

16ELSIF (clk'EVENT AND clk='1') THEN

17pr_state <= nx_state;

18END IF;

19END PROCESS;

20---------- Upper section: -----------------

21PROCESS (a, b, d, pr_state)

22BEGIN

23CASE pr_state IS

24WHEN stateA =>

25x <= a;

26IF (d='1') THEN nx_state <= stateB;

27ELSE nx_state <= stateA;

28END IF;

29WHEN stateB =>

30x <= b;

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Figure 8.5

Simulation results of example 8.2

31IF (d='1') THEN nx_state <= stateA;

32ELSE nx_state <= stateB;

33END IF;

34END CASE;

35END PROCESS;

36END simple_fsm;

37----------------------------------------------

Simulation results relative to the code above are shown in figure 8.5. Notice that the circuit works as expected. Indeed, looking at the report files, one will verify that, as expected, only one flip-flop was required to implement this circuit because there are only two states to be encoded. Notice also that the upper section is indeed combinational, for the output (x), which in this case does depend on the inputs (a or b, depending on which state the machine is in), varies when a or b vary, regardless of clk. If a synchronous output were required, then design style #2 should be employed.

8.3 Design Style #2 (Stored Output)

As we have seen, in design style #1 only pr_state is stored. Therefore, the overall circuit can be summarized as in figure 8.6(a). Notice that in this case, if it is a Mealy machine (one whose output is dependent on the current input), the output might change when the input changes (asynchronous output).

In many applications, the signals are required to be synchronous, so the output should be updated only when the proper clock edge occurs. To make Mealy machines synchronous, the output must be stored as well, as shown in figure 8.6(b). This structure is the object of design style #2.

To implement this new structure, very few modifications are needed. For example, we can use an additional signal (say, temp) to compute the output value (upper sec-

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Figure 8.6

Circuit diagrams for (a) Design Style #1 and (b) Design Style #2.

tion), but only pass its value to the actual output signal when a clock event occurs (lower section). These modifications can be observed in the template shown below.

State Machine Template for Design Style #2

LIBRARY ieee;

USE ieee.std_logic_1164.all;

-------------------------------------------------------

ENTITY <ent_name> IS

PORT (input: IN <data_type>; reset, clock: IN STD_LOGIC; output: OUT <data_type>);

END <ent_name>;

-------------------------------------------------------

ARCHITECTURE <arch_name> OF <ent_name> IS

TYPE states IS (state0, state1, state2, state3, ...); SIGNAL pr_state, nx_state: states;

SIGNAL temp: <data_type>; BEGIN

---------- Lower section: --------------------------

PROCESS (reset, clock) BEGIN

IF (reset='1') THEN pr_state <= state0;

ELSIF (clock'EVENT AND clock='1') THEN output <= temp;

pr_state <= nx_state; END IF;

END PROCESS;

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---------- Upper section: --------------------------

PROCESS (pr_state) BEGIN

CASE pr_state IS WHEN state0 =>

temp <= <value>;

IF (condition) THEN nx_state <= state1;

...

END IF; WHEN state1 =>

temp <= <value>;

IF (condition) THEN nx_state <= state2;

...

END IF; WHEN state2 =>

temp <= <value>;

IF (condition) THEN nx_state <= state3;

...

END IF;

...

END CASE; END PROCESS; END <arch_name>;

Comparing the template of design style #2 with that of design style #1, we verify that the only di¤erences are those related to the introduction of the internal signal temp. This signal will cause the output of the state machine to be stored, for its value is passed to the output only when clk’EVENT occurs.

Example 8.3: Simple FSM #2

Let us consider the design of example 8.2 once again. However, let us say that now we want the output to be synchronous (to change only when clock rises). Since this is a Mealy machine, design style #2 is required.

1 ----------------------------------------------

2ENTITY simple_fsm IS

3PORT ( a, b, d, clk, rst: IN BIT;

8TYPE state IS (stateA, stateB);

9 SIGNAL pr_state, nx_state: state;

10 SIGNAL temp: BIT;

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11BEGIN

12----- Lower section: ----------------------

13PROCESS (rst, clk)

14BEGIN

15IF (rst='1') THEN

16pr_state <= stateA;

17ELSIF (clk'EVENT AND clk='1') THEN

18x <= temp;

19pr_state <= nx_state;

20END IF;

21END PROCESS;

22---------- Upper section: -----------------

23PROCESS (a, b, d, pr_state)

24BEGIN

25CASE pr_state IS

26WHEN stateA =>

27temp <= a;

28IF (d='1') THEN nx_state <= stateB;

29ELSE nx_state <= stateA;

30END IF;

31WHEN stateB =>

32temp <= b;

33IF (d='1') THEN nx_state <= stateA;

34ELSE nx_state <= stateB;

35END IF;

36END CASE;

37END PROCESS;

38END simple_fsm;

39----------------------------------------------

Looking at the report files produced by the compiler, we observe that two flip-flops were now inferred, one to encode the states of the machine, and the other to store the output.

Simulation results are shown in figure 8.7. Recall that when a signal is stored, its value will necessarily remain static between two consecutive clock edges. Therefore, if the input (a or b in the example above) changes during this interval, the change might not be observed by the circuit; moreover, when observed, it will be delayed with respect to the input (which is proper of synchronous circuits).

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Figure 8.7

Simulation results of example 8.3.

d=1

d=1

Figure 8.8

States diagram for example 8.4.

Example 8.4: String Detector

We want to design a circuit that takes as input a serial bit stream and outputs a ‘1’ whenever the sequence ‘‘111’’ occurs. Overlaps must also be considered, that is, if . . .

0111110 . . . occurs, than the output should remain active for three consecutive clock cycles.

The state diagram of our machine is shown in figure 8.8. There are four states, which we called zero, one, two, and three, with the name corresponding to the number of consecutive ‘1’s detected. The solution shown below utilizes design style #1.

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1 --------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 --------------------------------------------

5ENTITY string_detector IS

6PORT ( d, clk, rst: IN BIT;

11TYPE state IS (zero, one, two, three);

12SIGNAL pr_state, nx_state: state;

13BEGIN

14----- Lower section: --------------------

15PROCESS (rst, clk)

16BEGIN

17IF (rst='1') THEN

18pr_state <= zero;

19ELSIF (clk'EVENT AND clk='1') THEN

20pr_state <= nx_state;

21END IF;

22END PROCESS;

24PROCESS (d, pr_state)

25BEGIN

26CASE pr_state IS

27WHEN zero =>

28q <= '0';

29IF (d='1') THEN nx_state <= one;

30ELSE nx_state <= zero;

31END IF;

32WHEN one =>

33q <= '0';

34IF (d='1') THEN nx_state <= two;

35ELSE nx_state <= zero;

36END IF;

37WHEN two =>

38q <= '0';

39IF (d='1') THEN nx_state <= three;

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40ELSE nx_state <= zero;

41END IF;

42WHEN three =>

43q <= '1';

44IF (d='0') THEN nx_state <= zero;

45ELSE nx_state <= three;

46END IF;

47END CASE;

48END PROCESS;

49END my_arch;

50--------------------------------------------

Notice that in this example the output does not depend on the current input. This fact can be observed in lines 28, 33, 38, and 43 of the code above, which show that all assignments to q are unconditional (that is, do not depend on d). Therefore, the output is automatically synchronous (a Moore machine), so the use of design style #2 is unnecessary. The circuit requires two flip-flops, which encode the four states of the state machine, from which q is computed.

Simulation results are shown in figure 8.9. As can be seen, the data sequence d ¼ ‘‘011101100’’ was applied to the circuit, resulting the response q ¼ ‘‘000100000’’ at the output.

Example 8.5: Tra‰c Light Controller (TLC)

As mentioned earlier, digital controllers are good examples of circuits that can be e‰ciently implemented when modeled as state machines. In the present example, we want to design a TLC with the characteristics summarized in the table of figure 8.10, that is:

Three modes of operation: Regular, Test, and Standby.

Regular mode: four states, each with an independent, programmable time, passed to the circuit by means of a CONSTANT.

Test mode: allows all pre-programmed times to be overwritten (by a manual switch) with a small value, such that the system can be easily tested during maintenance (1 second per state). This value should also be programmable and passed to the circuit using a CONSTANT.

Standby mode: if set (by a sensor accusing malfunctioning, for example, or a manual switch) the system should activate the yellow lights in both directions and remain so while the standby signal is active.

Assume that a 60 Hz clock (obtained from the power line itself ) is available.

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Figure 8.9

Simulation results of example 8.4.

timeGR

timeRG

Figure 8.10

Specifications and states diagram (regular mode) for example 8.5.

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