Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

Here, design style #1 can be employed, as shown in the code below.

1 -------------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 -------------------------------------------------

5ENTITY tlc IS

6PORT ( clk, stby, test: IN STD_LOGIC;

11CONSTANT timeMAX : INTEGER := 2700;

12CONSTANT timeRG : INTEGER := 1800;

13CONSTANT timeRY : INTEGER := 300;

14CONSTANT timeGR : INTEGER := 2700;

15CONSTANT timeYR : INTEGER := 300;

16CONSTANT timeTEST : INTEGER := 60;

17TYPE state IS (RG, RY, GR, YR, YY);

18SIGNAL pr_state, nx_state: state;

19SIGNAL time : INTEGER RANGE 0 TO timeMAX;

20BEGIN

21-------- Lower section of state machine: ----

22PROCESS (clk, stby)

23VARIABLE count : INTEGER RANGE 0 TO timeMAX;

24BEGIN

25IF (stby='1') THEN

26pr_state <= YY;

27count := 0;

28ELSIF (clk'EVENT AND clk='1') THEN

29count := count + 1;

30IF (count = time) THEN

31pr_state <= nx_state;

32count := 0;

33END IF;

34END IF;

35END PROCESS;

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36-------- Upper section of state machine: ----

37PROCESS (pr_state, test)

38BEGIN

39CASE pr_state IS

40WHEN RG =>

41r1<='1'; r2<='0'; y1<='0'; y2<='0'; g1<='0'; g2<='1';

42nx_state <= RY;

43IF (test='0') THEN time <= timeRG;

44ELSE time <= timeTEST;

45END IF;

46WHEN RY =>

47r1<='1'; r2<='0'; y1<='0'; y2<='1'; g1<='0'; g2<='0';

48nx_state <= GR;

49IF (test='0') THEN time <= timeRY;

50ELSE time <= timeTEST;

51END IF;

52WHEN GR =>

53r1<='0'; r2<='1'; y1<='0'; y2<='0'; g1<='1'; g2<='0';

54nx_state <= YR;

55IF (test='0') THEN time <= timeGR;

56ELSE time <= timeTEST;

57END IF;

58WHEN YR =>

59r1<='0'; r2<='1'; y1<='1'; y2<='0'; g1<='0'; g2<='0';

60nx_state <= RG;

61IF (test='0') THEN time <= timeYR;

62ELSE time <= timeTEST;

63END IF;

64WHEN YY =>

65r1<='0'; r2<='0'; y1<='1'; y2<='1'; g1<='0'; g2<='0';

66nx_state <= RY;

67END CASE;

68END PROCESS;

69END behavior;

70----------------------------------------------------

The expected number of flip-flops required to implement this circuit is 15; three to store pr_state (the machine has five states, so three bits are needed to encode

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them), plus twelve for the counter (it is a 12-bit counter, for it must count up to timeMAX ¼ 2700).

Simulation results are shown in figure 8.11. In order for the results to fit properly in the graphs, we adopted small time values, with all CONSTANTS equal to 3 except timeTEST, which was made equal to 1. Therefore, the system is expected to change state every three clock cycles when in Regular operation, or every clock cycle if in Test mode. These two cases can be observed in the first two graphs of figure 8.11, respectively. The third graph shows the Standby mode being activated. As expected, stby is asynchronous and has higher priority than test, causing the system to stay in state YY (state 4) while stby is active. The test signal, on the other hand, is synchronous, but does not need to wait for the current state timing to finish to be activated, as can be observed in the second graph.

Example 8.6: Signal Generator

We want to design a circuit that, from a clock signal clk, gives origin to the signal outp shown in figure 8.12(a). Notice that the circuit must operate at both edges (rising and falling) of clk.

To circumvent the two-edge aspect (section 6.9), one alternative is to implement two machines, one that operates exclusively at the positive transition of clk and another that operates exclusively at the negative edge, thus generating the intermediate signals out1 and out2 presented in figure 8.12(b). These signals can then be ANDed to give origin to the desired signal outp. Notice that this circuit has no external inputs (except for clk, of course), so the output can only change when clk changes (synchronous output).

1 -----------------------------------------

2ENTITY signal_gen IS

3PORT ( clk: IN BIT;

5END signal_gen;

6 -----------------------------------------

7ARCHITECTURE fsm OF signal_gen IS

8TYPE state IS (one, two, three);

9 SIGNAL pr_state1, nx_state1: state;

10SIGNAL pr_state2, nx_state2: state;

11SIGNAL out1, out2: BIT;

12BEGIN

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Figure 8.11

Simulation results of example 8.5.

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clk outp

(a)

(b)

Figure 8.12

Waveforms of example 8.6: (a) signal outp to be generated from clk and (b) intermediate signals out1 and out2 (outp ¼ out1 AND out2).

13----- Lower section of machine #1: ---

14PROCESS(clk)

15BEGIN

16IF (clk'EVENT AND clk='1') THEN

17pr_state1 <= nx_state1;

18END IF;

19END PROCESS;

20----- Lower section of machine #2: ---

21PROCESS(clk)

22BEGIN

23IF (clk'EVENT AND clk='0') THEN

24pr_state2 <= nx_state2;

25END IF;

26END PROCESS;

27---- Upper section of machine #1: -----

28PROCESS (pr_state1)

29BEGIN

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30CASE pr_state1 IS

31WHEN one =>

32out1 <= '0';

33nx_state1 <= two;

34WHEN two =>

35out1 <= '1';

36nx_state1 <= three;

37WHEN three =>

38out1 <= '1';

39nx_state1 <= one;

40END CASE;

41END PROCESS;

42---- Upper section of machine #2: -----

43PROCESS (pr_state2)

44BEGIN

45CASE pr_state2 IS

46WHEN one =>

47out2 <= '1';

48nx_state2 <= two;

49WHEN two =>

50out2 <= '0';

51nx_state2 <= three;

52WHEN three =>

53out2 <= '1';

54nx_state2 <= one;

55END CASE;

56END PROCESS;

57outp <= out1 AND out2;

58END fsm;

59------------------------------------------

Simulation results from the circuit synthesized with the code above are shown in figure 8.13.

8.4Encoding Style: From Binary to OneHot

To encode the states of a state machine, we can select one among several available styles. The default style is binary. Its advantage is that it requires the least number of

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Figure 8.13

Simulation results of example 8.6.

Table 8.1

State encoding of an 8-state FSM.

flip-flops. In this case, with n flip-flops (n bits), up to 2n states can be encoded. The disadvantage of this encoding scheme is that it requires more logic and is slower than the others.

At the other extreme is the onehot encoding style, which uses one flip-flop per state. Therefore, it demands the largest number of flip-flops. In this case, with n flip-flops (n bits), only n states can be encoded. On the other hand, this approach requires the least amount of extra logic and is the fastest.

An style that is inbetween the two styles above is the twohot encoding scheme, which presents two bits active per state. Therefore, with n flip-flops (n bits), up to n(n 1)/2 states can be encoded.

The onehot style is recommended in applications where flip-flops are abundant, like in FPGAs (Field Programmable Gate Arrays). On the other hand, in ASICs (Application Specific Integrated Circuits) the binary style is generally preferred.

As an example, say that our state machine has eight states. Then the encoding would be that shown table 8.1. The number of flip-flops required in each case is three (for binary), five (twohot), or eight (onehot). Other details are also presented in the table.

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Figure P8.1

8.5Problems

Each solution to the problems proposed below should be accompanied by synthesis and simulation results. Verify, at least, the following: number of flip-flops inferred and circuit functionality.

Problem 8.1: FSM

Write a VHDL code that implements the FSM described by the states diagram of figure P8.1.

Problem 8.2: Signal Generator #1

Using the FSM approach, design a circuit capable of generating the two signals depicted in figure P8.2 (out1, out2) from a clock signal clk. The signals are periodic and have the same period. However, while one changes only at the rising edge of clk, the other has changes at both edges.

Problem 8.3: Signal Generator #2

Design a finite state machine capable of generating two signals, UP and DOWN, as illustrated in figure P8.3. These signals are controlled by two inputs, GO and STOP. When GO changes from ‘0’ to ‘1’, the output UP must go to ‘1’ too, but T ¼ 10 ms later. If GO returns to ‘0’, then UP must return to ‘0’ immediately. However, the output DOWN must now go to ‘1’, again 10 ms later, returning to ‘0’ immediately if

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clk

out1

out2

1 period

Figure P8.2

GO

DOWN

clk

STOP

GO

UP

T

DOWN

Figure P8.3

GO changes to ‘1’. If the input STOP is asserted, then both outputs must go to ‘0’ immediately and unconditionally. Assume that a 10 kHz clock is available.

Problem 8.4: Keypad Debouncer and Encoder

Consider the keypad shown in the diagram of figure P8.4. A common way of reading a key press is by means of a technique called scanning or polling, which reduces the number of wires needed to interconnect the keypad to the main circuit. It consists of sending one column low at a time, while reading each row sequentially. If a key is pressed, then the corresponding row will be low, while the others remain high (due to the pull-up resistors).

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VDD

Figure P8.4

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