Файл: Circuit Design with VHDL (A.Pedroni, 2004).pdf

Encoding: Each digit must be encoded using the ASCII code (7 bits, with the corresponding hexadecimal values listed in the table of figure P8.4). When a new reading is available at the output, the new_data bit should be set to ‘1’. This will avoid interpreting a key pressed for a long time as a long series of the same character.

Debouncing: A problem inherent to mechanical switches is switch bounces, which occur before a firm contact is finally established. The settling generally takes up to a few milliseconds. Therefore, the choice of the clock frequency is very important. You are asked to choose it such that at least three readings occur in a 5 ms interval. Thus the new_data bit should be turned high only when the same result is obtained in all consecutive readings within a 5 ms interval.

Problem 8.5: Tra‰c Light Controller

Using your synthesis tool plus a CPLD/FPGA development kit, implement the TLC of example 8.5. Verify, in the report files generated by your software, which pins of the chip were assigned to the inputs (clk, stby, test) and to the outputs (r1, y1, g1, r2, y2, g2). Then make the following physical connections in your board:

a 60 Hz square wave signal (from a signal generator), with the appropriate logic levels, to the clk pin.

a VDD/GND switch to pin stby.

a VDD/GND switch to pin test.

an LED (red, if possible), with a 330-1kohm series resistor, to pin r1 (resistor connected between r1 and the anode of the LED, and cathode connected to GND).

an LED (yellow, if possible) to pin y1, with a series resistor like above.

an LED (green, if possible) to pin g1, with a series resistor like above.

finally, install other 3 LEDs, like those above, for r2, y2, and g2.

Now download the program file from your PC to the development kit and verify the operation of the TLC. Play with the switches in order to test all modes of operation. You can also increase the clock frequency to speed up the transition from red to yellow, etc.

Problem 8.6: Signal Generator #3

Solve problem 8.2 without using the finite state machine approach.

Problem 8.7: Signal Generator #4

Solve example 8.6 without using the FSM approach.

For further work is this area, see problems 9.3, 9.4, and 9.6 of chapter 9.

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9 Additional Circuit Designs

In the preceding chapters, we saw a series of complete design examples utilizing VHDL code. Each design included:

Top-level diagram of the circuit, with description;

Review of basic concepts whenever necessary;

Complete VHDL code;

Simulation results; and

Additional comments when needed.

This chapter concludes Part I of the book. In it, a series of additional design examples are presented. These examples, like all the other designs shown so far, are also at the circuit level (that is, self-contained in the main code). In Part II, we will do the same; that is, we will conclude Part II with a chapter containing additional system design examples.

The designs presented in this chapter are the following:

Barrel shifter (section 9.1)

Signed and unsigned comparators (section 9.2)

Carry ripple and carry look ahead adders (section 9.3)

Fixed-point division (section 9.4)

Vending machine controller (section 9.5)

Serial data receiver (section 9.6)

Parallel-to-serial converter (section 9.7)

Playing with a SSD (section 9.8)

Signal generators (section 9.9)

Memories (section 9.10)

Finally, a list of problems is also included (section 9.11).

Note: A complete list of all designs presented in the book is shown in section 1.5.

9.1Barrel Shifter

The diagram of a barrel shifter is shown in figure 9.1. The input is an 8-bit vector. The output is a shifted version of the input, with the amount of shift defined by the ‘‘shift’’ input (from 0 to 7). The circuit consists of three individual barrel shifters, each similar to that seen in example 6.9. Notice that the first barrel has only one ‘0’

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Figure 9.1

Barrel shifter.

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Figure 9.2

Simulation results from barrel shifter of figure 9.1.

connected to one of the multiplexers (bottom left corner), while the second has two, and the third has four. For larger vectors, we would just keep doubling the number of ‘0’ inputs. If shift ¼ ‘‘001’’, for example, then only the first barrel should cause a shift; on the other hand, if shift ¼ ‘‘111’’, then all barrels should cause a shift.

A VHDL code for the circuit of figure 9.1 is presented below. Simulation results, verifying the functionality of the circuit, are shown in figure 9.2. As can be seen in the latter, the output is equal to the input when shift ¼ 0 (that is, shift ¼ ‘‘000’’). It can also be seen that, as long as no bit of value ‘1’ is shifted out of the barrel, the output is equal to the input multiplied by 2 (1 shift) when shift ¼ 1 (‘‘001’’), multiplied by 4 (2 shifts) when shift ¼ 2 (‘‘010’’), multiplied by 8 (3 shifts) when shift ¼ 3 (‘‘011’’), and so on.

1 ---------------------------------------------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ---------------------------------------------

5ENTITY barrel IS

6PORT ( inp: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

7shift: IN STD_LOGIC_VECTOR (2 DOWNTO 0);

12BEGIN

13PROCESS (inp, shift)

14VARIABLE temp1: STD_LOGIC_VECTOR (7 DOWNTO 0);

15VARIABLE temp2: STD_LOGIC_VECTOR (7 DOWNTO 0);

16BEGIN

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17---- 1st shifter -----

18IF (shift(0)='0') THEN

19temp1 := inp;

20ELSE

21temp1(0) := '0';

22FOR i IN 1 TO inp'HIGH LOOP

23temp1(i) := inp(i-1);

24END LOOP;

25END IF;

26---- 2nd shifter -----

27IF (shift(1)='0') THEN

28temp2 := temp1;

29ELSE

30FOR i IN 0 TO 1 LOOP

31temp2(i) := '0';

32END LOOP;

33FOR i IN 2 TO inp'HIGH LOOP

34temp2(i) := temp1(i-2);

35END LOOP;

36END IF;

37---- 3rd shifter -----

38IF (shift(2)='0') THEN

39outp <= temp2;

40ELSE

41FOR i IN 0 TO 3 LOOP

42outp(i) <= '0';

43END LOOP;

44FOR i IN 4 TO inp'HIGH LOOP

45outp(i) <= temp2(i-4);

46END LOOP;

47END IF;

48END PROCESS;

49END behavior;

50---------------------------------------------

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Figure 9.3

Comparator.

9.2Signed and Unsigned Comparators

Figure 9.3 shows the top-level diagram of a comparator. The size of the vectors to be compared is generic (n þ 1). Three outputs must be provided: one corresponding to a > b, another to a ¼ b, and finally one relative to a < b. Three solutions are presented: the first considers a and b as signed numbers, while the other two consider them as unsigned values. Simulation results are also included.

Signed Comparator

Notice the presence of the std_logic_arith package in the code below (line 4), which is necessary to operate with SIGNED (or UNSIGNED) data types (a and b were declared as SIGNED numbers in line 8).

1 ---- Signed Comparator: ----------------

2LIBRARY ieee;

3USE ieee.std_logic_1164.all;

6ENTITY comparator IS

7GENERIC (n: INTEGER := 7);

8PORT (a, b: IN SIGNED (n DOWNTO 0);

13BEGIN

14x1 <= '1' WHEN a > b ELSE '0';

15x2 <= '1' WHEN a = b ELSE '0';

16x3 <= '1' WHEN a < b ELSE '0';

17END signed;

18 ----------------------------------------

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Figure 9.4

Simulation result of signed comparator of figure 9.3.

Simulation results are shown in figure 9.4. As can be seen, 127 > 0, but 128 < 0 and also 255 < 0 (because in 2’s complement notation 127 is the decimal 127 itself, but 128 is the decimal 128, and 255 is indeed 1).

Unsigned Comparator #1

The VHDL code below is the counterpart of the code just presented (signed comparator). Notice again the presence of the std_logic_arith package (line 4), which is necessary to operate with UNSIGNED (or SIGNED) data types (a and b were declared as UNSIGNED numbers in line 8).

1 ---- Unsigned Comparator #1: -----------

2LIBRARY ieee;

3USE ieee.std_logic_1164.all;

6ENTITY comparator IS

7GENERIC (n: INTEGER := 7);

8 PORT (a, b: IN UNSIGNED (n DOWNTO 0);

9 x1, x2, x3: OUT STD_LOGIC);

10 END comparator;

11 ----------------------------------------

12 ARCHITECTURE unsigned OF comparator IS

13BEGIN

14x1 <= '1' WHEN a > b ELSE '0';

15x2 <= '1' WHEN a = b ELSE '0';

16x3 <= '1' WHEN a < b ELSE '0';

17END unsigned;

18 ----------------------------------------

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Figure 9.5

Simulation result of unsigned comparator of figure 9.3.

Unsigned Comparator #2

Unsigned comparators can also be implemented with STD_LOGIC_VECTORS, in which case there is no need to declare the std_logic_arith package. A solution of this kind is presented below.

1 ---- Unsigned Comparator #2: -----------

2LIBRARY ieee;

3 USE ieee.std_logic_1164.all;

4 ----------------------------------------

5ENTITY comparator IS

6GENERIC (n: INTEGER := 7);

7PORT (a, b: IN STD_LOGIC_VECTOR (n DOWNTO 0);

12BEGIN

13x1 <= '1' WHEN a > b ELSE '0';

14x2 <= '1' WHEN a = b ELSE '0';

15x3 <= '1' WHEN a < b ELSE '0';

16END unsigned;

17 ----------------------------------------

Simulation results (from either unsigned comparator) are shown in figure 9.5. Contrary to figure 9.4, now 128 and 255 are indeed bigger than zero.

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