Файл: Microcontrollers in Practice (Mitescu M., 2005).pdf

50 4 Using the Synchronous Serial Interface SPI

Internal bus

Fig. 4.2. General block diagram of the SPI

When the MASTER writes by software a byte into the transmitter’s data register, eight clocks are automatically generated to the SCK line, and the bi-directional transmission begins. Whatever is found at this moment in the SLAVE’s Tx Data Register is shifted into the MASTER’s Rx Data Register.

When more than one SLAVE device is connected to the SPI bus, only one SLAVE may be enabled at a certain time. An additional signal SS (SLAVE Select), active LOW, is used to select the active SLAVE device.

4.3 The SPI of HC11 Microcontrollers

The structure of the SPI of HC11 follows exactly the general structure of a peripheral interface, shown in Fig. 1.6. The registers of the interface are called SPDR (SPI Data Register), SPCR (SPI Control Register), and SPSR (SPI Status Register).

SPDR – SPI Data Register

When writing to the address of SPDR, data is directly written into the transmitter’s shift register. Reading from this address actually reads the last byte received in the receivers shift register. SPDR is double buffered for input, and single buffered for output. This means that SPDR can be read while a data transfer is in progress, but if a byte is written into SPDR before the transmission of the previous character is completed, an error condition occurs.

SPSR – SPI Status Register

The status register has the following structure:

•SPIF – SPI transfer complete flag. This flag is set when a SPI transfer is complete

(after eight SCK cycles in a data transfer). It is cleared by reading SPSR (with SPIF = 1), then accessing (reading or writing) SPDR.

SPIF = 0 No SPI transfer complete or SPI transfer still in progress SPIF = 1 SPI transfer complete

•WCOL – Write Collision. This is an error flag. It is set if the software tries to

write data into SPDR while SPI data transfer is in progress. Clear this flag by reading SPSR (WCOL = 1), then access SPDR.

WCOL = 0 No write collision WCOL = 1 Write collision

•MODF – Mode Fault. This is another error flag. This error occurs when the input line SS is pulled LOW (the device is hardware configured as SLAVE) while the bit MSTR in the control register SPCR is set to 1.

This type of error occurs in multi-MASTER networks when more than one device is trying to become MASTER at a certain moment.

All other bits of SPSR are not implemented and always read 0. Out of RESET, SPSR is cleared.

SPCR – SPI Control Register

•SPIE – SPI Interrupt Enable. When set to 1, this bit enables interrupt requests from the SPI system.

SPIE = 0 SPI system interrupts disabled SPIE = 1 SPI system interrupts enabled

SPI can generate interrupts in two situations:

–Each time the SPIF bit in SPSR is 1 (a serial data transfer is completed).

–Each time MODF is set.

SPE – Serial Peripheral System Enable

SPE = 0 SPI system disabled

SPE = 1 SPI system enabled

This control bit enables the whole SPI system and assigns port D bits 2, 3, 4, 5 to SPI. If the SPI works in master mode and DDRD bit 5 is set, then the port D bit 5 pin becomes a general-purpose output line instead of the SS input.

52 4 Using the Synchronous Serial Interface SPI

•DWOM – Port D Wired-OR Mode. This bit selects the type of output on PORT D. DWOM affects all port D pins. This bit is not directly related to the SPI. It is placed here because the SPI uses most of the PORTD bits.

DWOM = 0 PORTD is configured as normal CMOS outputs

DWOM = 1 PORTD has open-drain outputs

•MSTR – Master Mode Select. This bit must be set by software to configure the device to work as MASTER for the SPI link.

•CPOL – Clock Polarity

CPOL = 0 SCK line idles LOW CPOL = 1 SCK line idles HIGH

•CPHA – Clock Phase

CPHA = 0 SS must go HIGH between successive characters transmitted. CPHA = 1 SS can be maintained LOW for all transfers

CPOL and CPHA must be programmed with identical values for MASTER and SLAVE

•SPR[1:0] – SPI Clock Rate Selects

When the device is configured as MASTER, these two bits select how the SPI clock (SCK) is obtained by dividing the main clock E, as described in Table 4.1. When the device is configured as SLAVE, these bits have no effect, because the MASTER generates the clock SCK.

Table 4.1. The effect of programming [SPR1–SPR0]

Initialization of the Interface

Obviously, the initialization sequence is different for MASTER and SLAVE. Below is an example of an initialization sequence. Note that the SPI system interrupts are enabled at the SLAVE device.

56 4 Using the Synchronous Serial Interface SPI

*SPI_SENDCH - sends character stored at XSPI over SPI

*returns the character received form SLAVE in RSPI

Note that, at each interrupt, the SLAVE prepares the data to be delivered to MASTER at the next interrupt. The main program is responsible for preparing the transmission data in the variable SPIXDATA, according to the value received from MASTER in SPIRDATA. QSPI is a flag indicating that a character has been received and placed in SPIRDATA by the interrupt service routine.

4.5.2 Expanding the I/O Space Using the SPI

In some cases, when the number of MCU I/O lines is insufficient for a certain application, a possible solution to expand the I/O space is to use shift registers connected to the SPI. The following example shows how the I/O space of an ATMega8 AVR is expanded with one 8-bit input port, and one 8-bit output port. For the input port, a parallel-input serial-output shift register (74165) is used. The output port is implemented using a 4094 serial-input parallel-output register. The schematic of the circuit is presented in Fig. 4.4.

Obviously, in this SPI link, the MASTER device is the microcontroller. The serial data input of register IC2 is connected to the MOSI line of the MCU. The shift clock for this register is generated by the microcontroller on the SCK line. The load (LD) input for the 4094 register is driven by an extra output line of the micrcontroller (PB2).