Файл: Microcontrollers in Practice (Mitescu M., 2005).pdf

6.5.6 Using Timer1 as a Baud Rate Generator

Timer1 is used to generate the communication clock for the serial port. When the serial port is configured in mode 1 or 3, the baud rate is determined by the Timer1 overflow rate, according to the following formulas (SMOD is bit 7 in PCON):

When SMOD = 0 Baud = (Timer1_Overflow_Rate)/32

When SMOD = 1 Baud = (Timer1_Overflow_Rate)/16

Both internal or external clock sources may be selected; the only thing that counts is the overflow rate. In practice, for the usual baud rates, the use of the internal clock is recommended, and to program Timer1 in mode 2, autoreload. The software initialization sequence loads TH1 with the reload value and starts the timer. No further action is required for the software.

Timer0 can be configured to operate in mode 3, and use the control signals TF1, TR1, while Timer1 is used as baud rate generator.

Compared to the AVR and HC11 timers, the general-purpose timer of the 8051 is weaker, for at least two reasons:

•The only event related to the timer reported to the CPU is timer overflow

•The timer cannot directly control any of the MCU I/O lines.

These minuses have been corrected in the next generation of microcontrollers derived from 8051. The 80x52 family of microcontrollers includes an additional timer, called Timer2, which solves these problems.

6.5.7 Exercises for Programming the 8051 Timer

SX 6.6

Starting from an oscillator frequency of 11.059 MHz, write an initialization sequence to use Timer1 as a baud rate generator for 9600 baud.

Solution

The frequency of the internal clock is: fCOUNT = fOSC/12 = 0.92158 MHz. The frequency of the UART clock is: fUART = 16×Baud_rate = 16×9600 = 153 600 Hz.

The resulting overflow rate for Timer1 is:

Timer1_Overflow_Rate = fCOUNT/ fUART = 6 .

This gives the reload value for Timer1:

(TH1) = 255 − 6 + 1 = 250 = 0xFA .

The other initializations required refer to:

•SMOD (bit 7 of PCON) must be set to 1

•Select operating mode 2 for Timer1 (M1 = 1, M0 = 0)

•Select the internal clock for Timer1 (C/T = 0)

•Start the timer (TR1 = 1)

86 6 Using the MCU Timers

The resulting values for the registers involved are: PCON = 80h, TMOD = 20h, and TCON = 40h.

Here is the initialization sequence required:

INIT_T1:

SX6.7

Starting from an oscillator clock frequency of 20 MHz, write the initialization sequence and the interrupt service routine to configure Timer0 in operating mode 1, to generate interrupts at 10-ms intervals.

Solution

In operating mode 1, with C/T = 0, T0 is a 16-bit counter, using the internal clock with a frequency of fCLOCK = fOSC/12, which corresponds to a period TCLOCK = 0.6 µs. The required 10-ms interval corresponds to a number of 10 000/0.6 = 16 666 TCLOCK periods. To overflow in 16 666 periods, the timer must start counting at the value: 65 535 − 16 666 + 1 = 48 870 = 0BEE6H.

The other initializations required concern selecting the operating mode 1 (M1 = 0, M0 = 1) in TMOD, and starting the timer, by setting TR1 = 1 in TCON. Finally the initialization sequence must enable a Timer0 interrupt, by setting the bits EA and ET0 in register IE. The interrupt service routine must reload the value 0BEE6H in TH0:TL0.

Here is the required initialization sequence:

The interrupt service routine must reload the initialization values in TH0:TL0. Since each MOV instruction takes two cycles to execute, the reload value must be decreased by 4, and becomes 0BEE2H.

MOV TH0,#0BEH ;TH0

MOV TL0,#0E2H ;TL0

in opposite directions, when TCNT1 matches the value of OCR1 when counting upwards, and downwards. Refer to Fig. 6.8, and 6.9 for details of the operation of the PWM AVR timer.

This PWM system is far less flexible than that of the HC11, but it is simple and cheap, so that it has been implemented in many AVR microcontrollers.

6.7 Watchdog Timers

The block diagram of a watchdog timer is presented in Fig. 6.10. The system consists of a counter, having the overflow time programmable in a range from a few milliseconds to a few seconds. When the watchdog overflows, a hardware RESET is generated.

CLK

RESET COUNTER

CONTROL

REGISTER

Internal bus

Fig. 6.10. Block diagram of the watchdog timer

If the watchdog is enabled, the program running on the microcontroller must be organized so that, periodically, at time intervals shorter than the overflow time, it resets the watchdog’s counter, otherwise a hardware RESET is generated.

The control register is used to enable the watchdog, to select the overflow time, and to reset the counter.

6.7.1 The Watchdog of HC11

The watchdog system of HC11 is called the COP Timer (Computer Operating Properly Timer).

The watchdog overflow time is selected by means of the control bits [CR1:CR0] (COP Rate select) in the OPTION register, as shown in Table 6.9. [CR1:CR0] can only be written during the first 64 E clock cycles, after RESET. This artifice is intended to prevent unintentional modification of the watchdog settings in case of program runaway.

For the same safety reason, the control bit that enables the whole watchdog system is the NOCOP bit in the CONFIG register. As mentioned before, CONFIG is a non-volatile, EEPROM type register, which can only be modified using special programming sequences, as described in Chap. 8.

A special register COPRST has been provided to clear the watchdog counter. This is cleared by writing bytes $55 and $AA, in this order, to COPSRT:

6.7.2 The Watchdog of AT90S8515

The watchdog of the AVR family counts on a separate clock, distinct from the MCU clock. This is generated by an internal RC oscillator and has an approximate frequency of 1 MHz at VCC = 5 V.

The software control on the watchdog system is performed by means of the WDCTR (Watchdog Control) register, which has the following structure:

[WDP2:WDP1:WDP0] – (Watchdog prescaler select) These bits determine the overflow time of the timer as shown in Table 6.10.

Before modifying [WDP2:WDP1:WDP0], it is recommended to disable or reset the watchdog, to avoid accidental activation.

The watchdog is enabled by writing 1 in the WDE (Watchdog Enable) bit. Disabling is more complicated, for safety reasons. An additional control bit WDTOE (Watchdog Turn-Off Enable) has been introduced Prior to clearing WDE, WDTOE and WDE must be both set to 1 in the same operation, and, in the next four cycles, WDE can be written with 0.