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•MULT – Multiple-channel/single-channel control.

MULT = 0 the conversions are made on a single-input channel, selected by the

[CD:CC:CB:CA] bits

MULT = 1 the conversions are executed on a four-channel group. In this case, the CB and CA selection bits have no effect and the conversions are performed on the four input group addressed by the CD:CC

•[CD:CC:CB:CA]-channel select. The CD bit is reserved for factory testing – always use CD = 0. The effect of the other three bits is described in Table 7.2.

7.5 Exercises on Programming the A/D Converter of HC11

SX 7.1

Write the initialization sequence that prepares the A/D subsystem to be used with the E clock, in single-channel conversion mode, single conversion cycle.

Solution

At RESET, the APDU bit from the OPTION register is cleared. The initialization sequence must set ADPU to 1 to power up the converter. The E clock is selected by erasing the CSEL bit. These initializations must be made after RESET, at least 10 ms before the first conversion cycle. For the other initializations: erasing the MULT bit to select the single-channel operating mode, and SCAN for single conversion cycle, can be made directly in the start conversion routine.

The required initialization routine is this:

SX 7.2

Write a subroutine that receives as input in A the address of the analog channel. The subroutine starts the conversion of the specified channel, waits for the end of conversion and returns the conversion result in A.

Solution

The conversion is automatically started by any write operation to the ADCTL register. CCF = 1 indicates the end of the conversion. When SCAN = 0, four consecutive conversions are performed on the same analog input. At the end of conversion, the four result registers ADR1–ADR4 contain the results of the four conversions. Here is the subroutine that performs the requested operations:

SX 7.3

Write a subroutine that starts the conversion and reads the AN4–AN7 channels, updating the variables ANALOG4–ANALOG7.

Solution

To execute a conversion cycle on a group of four inputs, the bit MULT in ADCTL must be set to 1. The inputs AN4–AN7 are selected by CC = 1 (when MULT = 1, CB and CA are ignored). The required control word for ADCTL is 00010100 = $14. To read the group AN0–AN3, the control word would be $10. The subroutine performing the requested tasks looks like this:

*MASTER SPI initialization routine

100 7 Interfacing to Analog Signals

STAA ANALOG6

LDAA ADR4

STAA ANALOG7

RTS

7.6 The A/D Converter of the AVR Microcontrollers

The AVR ADC has some distinguishing features, compared to HC11:

•10-bit resolution. Therefore, the conversion result is presented in two registers (ADCH:ADCL).

•The ADC can generate an interrupt request at the end of conversion.

•The ADC can operate while the CPU is in sleep mode. This reduces the errors caused by noise.

•A dedicated prescaler generates the ADC clock.

•The ADC can operate in two different modes: single conversion and free running.

When in free running operating mode the ADC works like the HC11 ADC with SCAN = 1. In single conversion mode, only the selected channel is converted, then the ADC halts until a new conversion is started by software.

Details on the Implementation of the ADC of AT90S8535

The control and status register of the A/D Converter, ADCSR, has the following structure:

•ADEN – AD Converter Enable. When ADEN = 1 the ADC is enabled. This bit is cleared at RESET, therefore it is required to set it to 1 in the initialization sequence.

•ADSC – A/D Start Conversion Command. Writing 1 to this bit starts the conversion. Once written with 1, the bit remains set until the end of the conversion. Writing 0 to this bit has no effect.

•ADFR – A/D Free Running Mode select. When set, this bit selects the free running operating mode. In this mode, the ADC permanently samples the input line and executes conversions.

•ADIF – A/D Interrupt Flag. This bit is set automatically at the end of a con-

version after the data registers have been updated. If the ADC interrupts are enabled (ADIE = 1) ADIF = 1 generates an interrupt request. ADIF is automatically cleared when executing the interrupt service routine, or by writing 1 in the corresponding position of ADCSR.

•ADIE – AD Interrupt Enable. When set to 1, this bit enables the interrupts from the ADC subsystem. The interrupt is generated at the end of the conversion, by the ADIF flag.

•[ADPS2:ADPS1:ADPS0] – AD Prescaller Select. The clock applied to the ADC subsystem is obtained by dividing the system clock using a prescaler.

These bits select the prescaler dividing rate according to Table 7.3.

The selection of the input upon which the conversion is executed is made by the ADMUX register. This has only three bits implemented, in the least significant positions.

[MUX2:MUX1:MUX0] Analog multiplexer selection bits. These bits instruct the analog multiplexer to select the input to be converted. [0:0:0] corresponds to ADC0, and so on; [1:1:1] selects ADC7.

Important note. The analog inputs of AT90S8535 use the I/O lines of PORTA. In principle, some of the A port lines can be configured as output lines. However, it is not recommended to activate these output lines while a conversion is in progress, because conversion errors can occur.

7.7 Exercises on Programming the A/D Converter AT90S8535

SX 7.4

Write the initialization sequence to select the ADC to operate using the clock frequency XTAL/2, in single conversion mode, with the interrupts enabled.

Solution

The control word to be written in ADCSR must contain the bits ADEN, ADIE and ADPS2 set to 1, the remaining bits being 0.