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8.3 The EEPROM Memory and the CONFIG Register of HC11 |
109 |
Table 8.2. Block addresses associated with BPRTi, valid for 68HC11F1
Bit name Block protected
BPRT0 $xE00–$xE1F
BPRT1 $xE20–$xE5F
BPRT2 $xE60–$xEDF
BPRT3 $xEE0–$xFFF
•PTCON – Protect CONFIG register. When this bit is set to 1, the CONFIG register cannot be written or erased.
•BPRT3–BPRT0 – When these bits are 1, the protection of an EEPROM memory block associated with each bit is activated, as shown in Table 8.2.
The BPROT register can only be written during the first 64 E cycles after RESET. Out of RESET, all BPROT bits are set to 1, which means that the protection is activated. The programming examples presented in the next paragraph assume that all bits of interest in the BPROT register have been erased in the initialization sequence, executed immediately after RESET.
8.3.2 Software Routines to Erase and Write the EEPROM
8.3.2.1 Erasing a Single Byte of EEPROM
The E2BE (EEPROM Byte Erase) subroutine receives in X the address of the byte to be erased. The first step is to write in PPROG a control word, which specifies an erase operation (EELAT = 1 and ERASE = 1) at the byte level (BYTE = 1). The next step is to perform a write operation to the address of the byte to be erased.
When EELAT = 1, the address of the destination of any write operation is stored in special latches, and will be used in further erase or write operations to EEPROM. The actual erase process starts when the EEPGM bit is set, and lasts about 10 milliseconds. After this delay, the PPROG register must be cleared to return to normal operation mode. Here is the subroutine that executes an EEPROM byte erase.
E2BE |
LDAB |
#$16 |
;BYTE=1, ERASE=1, EELAT=1 |
STAB |
PPROG |
||
STAB |
0,X |
;write operation to latch |
|
;address |
|||
LDAB |
#$17 |
;make EEPGM=1 |
|
STAB |
PPROG |
;start Vpp charge pump |
|
JSR |
DLY10 |
;wait 10 ms |
|
CLR |
PPROG |
;stop Vpp and return to |
|
read ;mode |
|||
RTS |
;return to main program |
110 8 Using the Internal EEPROM Memory
8.3.2.2 Writing a Byte to EEPROM
The E2W (EEPROM write) subroutine, listed below, assumes that:
E2W |
LDAB |
#$02 |
;BYTE=0, ERASE=0, EELAT=1 |
STAB |
PPROG |
||
STAA |
0,X |
;write operation to latch the |
|
;address and data |
|||
LDAB |
#$03 |
;make EEPGM=1 |
|
STAB |
PPROG |
;start Vpp charge pump |
|
JSR |
DLY10 |
;wait 10 ms |
|
CLR |
PPROG |
;stop Vpp and return to read |
|
;mode |
|||
RTS |
;return to main program |
•The bit in BPROT associated with the destination address of the write operation is cleared, i.e. the destination is not write protected.
•The destination byte has been previously erased.
•The address of the destination byte is placed in X.
•The data byte to be written in the EEPROM is placed in A.
If ERASE = 1 and BYTE = 0, setting PPROG will initiate an erase sequence on the entire EEPROM memory, called BULK ERASE.
Reading EEPROM while a write or erase operation is in progress (EELAT = 1) will return erroneous data. There is no hardware mechanism to prevent this type of error.
8.3.3 The CONFIG Register
The CONFIG register consists of eight EEPROM cells, organized as a register located in the I/O register block of the MCU. The CONFIG register can be erased or programmed just like any other EEPROM location. The structure of the CONFIG register of 68HC11F1 is as follows:
CONFIG |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
– |
– |
– |
– |
– |
NOCOP |
ROMON |
EEON |
|
RESET |
0 |
0 |
0 |
0 |
0 |
x |
x |
x |
•NOCOP = 1 disables the COP (Computer Operating Properly) watchdog,
•ROMON = 1 enables the internal ROM.
•EEON = 1 enables the internal EEPROM.
Some members of the HC11 family allow remapping of the EEPROM block to the beginning of any 4 K boundary in the memory map. To this purpose, the most significant four bits of the CONFIG registers, called [EE3:EE2:EE1:EE] are used to
8.4 The EEPROM Memory of the AVR Microcontrollers |
111 |
define the most significant four bits of the address of the EEPROM. For example, if [EE3:EE2:EE1:EE] = [0:1:0:1], then the starting address of the EEPROM is $5000.
Bulk erase operations on the EEPROM do not affect the CONFIG register.
A new value written to the CONFIG register becomes effective only after a subsequent RESET sequence.
8.4 The EEPROM Memory of the AVR Microcontrollers
There are significant differences in the way the EEPROM memory is implemented in AVR microcontrollers, compared to HC11. While in HC11, the EEPROM memory is directly visible in the memory map, and can be used as data memory or as program memory, for the AVRs the access to the EEPROM looks more like accessing data from a peripheral interface.
8.4.1 The Registers of the Interface with the EEPROM Memory
Four registers control the access to the EEPROM. These are named EEARH, EEARL, EEDR and EECR.
•EEARH – EEARL (EEPROM Address Register High/Low) form together a 16-bit register that implements the EEPROM address space.
•EEDR – EEPROM Data Register. This is used to access the EEPROM data, during the read and write operations.
•EECR – EEPROM Control Register contains the control bits for the write and read operations. EECR has the following structure:
EECR |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
– |
– |
– |
– |
– |
EEMWE |
EEWE |
EERE |
|
RESET |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
•EEMWE – EEPROM Master Write Enable. This bit provides a protection mechanism of the EEPROM data, in case of program runaway. The EEMWE is set by software, but is automatically cleared by hardware, after four cycles of the main system clock. In this interval of four cycles, it is possible to initiate a write
operation to the EEPROM, by writing 1 to EEWE. Attempts to write to EEWE when EEMWE = 0 have no effect. EEWE is cleared by hardware when the write operation completes, usually after 2.5–4 ms, depending on the value of the supply voltage. Therefore, it is recommended to poll EEWE, to determine the end of the write operation.
•EERE – EEPROM Read Enable. This bit selects the access type to the EEPROM.
EERE = 1 indicates a read operation, while EERE = 0 indicates a write operation.
112 8 Using the Internal EEPROM Memory
8.4.2 Software Routines to Read and Write EEPROM
8.4.2.1 Reading a Byte from EEPROM
The following program sequence reads in R16 an EEPROM byte from the address indicated by register Z. It starts by testing EEWE to determine if the interface is ready. If EEWE = 0 the contents of Z are transferred to EEARH–EEARL, then a control word is written to EECR having EERE = 1 (read operation). The EEPROM data is now readable in EEDR.
EERead:
SBIC |
EECR,EEWE |
;make sure EEWE=0 |
RJMP |
EERead |
|
OUT |
EEARH,ZH |
;write address in EEARH-EEARL |
OUT |
EEARL,ZL |
|
LDI |
R16,$01 |
;EERE=1 -- read operation |
OUT |
EECR, R16 |
|
IN |
R16,EEDR |
;read data in R16 |
RET |
8.4.2.2 Writing a Byte To EEPROM
The subroutine described below writes the byte in R16 to the EEPROM address specified by Z. The following sequence of operations is performed:
•Check EEWE to determine if the interface is ready.
•Write Z to EEARH:EEARL.
•Write R16 to EEDR.
•Set EEWME.
•Set EEWE to start the actual write operation.
Here is the program that executes these operations:
EEWrite:
SBIC |
EECR,EEWE |
;make sure EEWE=0 |
RJMP |
EEWrite |
|
OUT |
EEARH,ZH |
;write address in EEARH-EEARL |
OUT |
EEARL,ZL |
|
OUT |
EEDR,R16 |
;write data to EEDR |
CLI |
;disable interrupts |
|
LDI |
R16,$04 |
;EEMWE=1 |
OUT |
EECR, R16 |
|
LDI |
R16,$02 |
;EEWE=1 |
OUT |
EECR,R16 |
|
SEI |
;enable interrupts |
|
RET |