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A.8 AT90S8515 Operating with External RAM

Some AVR microcontrollers can allocate some of the I/O lines to extend the bus of the data memory for connecting external memory or other RAM-like external devices. Figure A8.1 presents an example of implementation of the external bus for the microcontroller AT90S8515.

MCU AT90S8515

39

D0

2

IC1

19

A0

10

IC2

11

D0

PA0/AD0

1D

1Q

A0

I/O0

9

12

PA1/AD1

38

D1

3

2D

2Q

18

A1

A1

I/O1

D1

8

13

PA2/AD2

37

D2

4

3D

3Q

17

A2

A2

I/O2

D2

7

15

PA3/AD3

36

D3

5

4D

4Q

16

A3

A3

I/O3

D3

6

16

PA4/AD4

35

D4

6

5D

5Q

15

A4

A4

I/O4

D4

5

17

PA5/AD5

34

D5

7

6D

6Q

14

A5

A5

I/O5

D5

4

18

PA6/AD6

33

D6

8

7D

7Q

13

A6

A6

I/O6

D6

3

19

PA7/AD7

32

D7

9

8D

8Q

12

A7

A7

I/O7

D7

25

ALE

11

C

A8

A8

30

A9

24

A9

ALE

1

OC

A10

21

A10

A11

23

A11

GND

74573

A12

2

A12

16

PD6/WR\

PC7/A15

28 A15

A13

26

A13

1

PC6/A14

27 A14

A14

A14

17

PD7/RD\

PC5/A13

26 A13

WR\

27

WE\

PC4/A12

25 A12

22

PC3/A11

24 A11

RD\

OE\

PC2/A10

23 A10

A15

20

CS\

PC1/A9

22 A9

21 A8

62256

PC0/A8

Fig. A8.1. AT90S8515 operating with external bus for data memory

In this example, the external memory is a 32K×8 62256 circuit, selected directly with the address line A15, which makes it visible in the address range $0000–$7FFF in the address space of the data memory.

The control signals for the external bus are generated by the MCU. ALE (Address Latch Enable) is active HIGH, and strobes the lower half of the address into the external address latch IC1 (74LS573), while RD\ (Read) and WR\ (Write) are active LOW and indicate the direction of the data transfer on the external bus. They are directly connected to the control inputs OE\ and WR\ of the external RAM circuit IC2.

A.9 In-system Programming the AVR AT90S8535

The internal flash and EEPROM memory of many of the AVR microcontrollers can be programmed “in system”, without removing the circuit from its socket, through the ISP (In-System Programming) interface. At the hardware level, the ISP interface uses the SPI lines MOSI, MISO and SCK to transfer data between the host and the device to be programmed. The ISP interface takes control of the SPI lines when the RESET input of the MCU is LOW.

Atmel Corporation offers a free software utility, called AVRISP, which allows the use of a personal computer to program the AVR microcontrollers through the ISP. Although the data transfer through the ISP is serial, the ISP interface is connected to the parallel port of the PC by means of a cable adapter. One possible implementation of the ISP cable adapter for the parallel port is presented in Fig. A9.1.

ENA

BSCK

BMOSI

10

BRST

IC1C

13

9

8

ISP Connector

25

12

(female)

11

24

10

23

1

IC1A

MOSI 1

Cable

9

22

2

RST

2

8

21

3

SCK

3

7

20

MISO 4

6

19

VCC

5

5

18

GND

6

4

17

4

IC1B

SV1

3

16

5

6

2

15

1

14

ENB

X1

13

IC1D

(male)

12

11

BMISO

74HC125

GND

Fig. A9.1. Schematic of the cable adapter between the parallel port of PC and the ISP

Figure A9.2 shows the layout of the PCB for this circuit. Note that the circuit is powered through the ISP cable.

For the ISP to operate, the MCU must be powered, and an external crystal must be present, for the oscillator. The XTAL frequency must be at least twice the frequency of the data transmission clock SCK.

X1

25

14 1

IC1

1

SV1

6

Fig. A9.2. Layout of the PCB for the ISP cable adapter

230 Appendices

The ISP protocol requires that 4-byte data packets be transferred through on the interface for each command. For example, the command consisting of the series of bytes [$AC, $53, xx, xx] (xx are “don’t care” bytes) instructs the MCU to enter programming mode. During the transmission of the third byte, the MCU echoes the value $53 received as the second byte of the packet to acknowledge the command.

The command to read a byte from the program memory has the following structure:

0010 H000

xxxx aaaa

bbbb bbbb

oooo oooo

H indicates which byte of the location of program memory specified by the bits aaaabbbbbbbb must be read. H = 1 addresses the most significant byte, H = 0 refers to the least significant byte. During the transmission of the fourth byte – oooooooo – the MCU returns the value read from the specified address of the flash memory.

The full list of commands of the ISP protocol is presented in Table A9.3.

To prevent unintentional programming of the flash or EEPROM memory while using the SPI interface, a special protection mechanism, called “lock bits”, has been provided. Lock bits are non-volatile bits, accessible only in programming mode, that inhibit further access to the EEPROM or flash memory in programming mode. AT90S8535 has two lock bits, LB1 and LB2, with the functions listed in Table A9.2.

Table A9.1. Functions of the lock bits of AT90S8535

Lock bits Protection type

LB1 LB2

11 No memory lock features enabled

01 Further programming of Flash and EEPROM disabled

00 Verify is also disabled

Once programmed with 0, the lock bits can only be brought to the erase value 1 through a chip erase operation.

Fuse bits are non-volatile control bits similar to the lock bits but with different functions. There are two fuse bits named SPIEN and FSTRT.

SPIEN – Serial Programming Enable. Its default value is 0 (enabled). This bit cannot be modified through ISP.

FSTRT – Short Start-up Time determines the duration of the internal RESET pulse, so that the external oscillator can settle. The operation of the watchdog timer is also delayed with a programmable number of cycles, as shown in Table A9.3.

When any of the lock bits is programmed (i.e. have the value 0) the access to the fuse bits is inhibited. Therefore, the fuse bits must be programmed first.

The ISP command Chip Erase brings the lock bits to the erased value (1) but does not affect the fuse bits.

A.9 In-system Programming the AVR AT90S8535

231

Table A9.2. The effect of the fuse bit FSTRT for AT80S8535

FSTRT

Internal RESET duration

Number of WDT cycles

at VCC = 5 V

Programmed

1.1 ms

1 K

Unprogrammed

16.0 ms

16 K

The signature bytes are three special read-only bytes that indicate the manufacturer, the size of the program memory and the device type. They are used by programmers to identify the devices. See the specific data sheets for the values of the signature bytes. When both the lock bits are programmed (0) the signature bytes are no longer accessible through the ISP interface.

Table A9.3. List of the ISP protocol commands

Command

Command format

Programming Enable

1010 1100

0101 0011

xxxx xxxx

xxxx xxxx

Chip Erase

1010 1100

100x xxxx

xxxx xxxx

xxxx xxxx

Read Program Memory

0010 H000

xxxx aaaa

bbbb bbbb

oooo oooo

Write Program Memory

0100 H000

xxxx aaaa

bbbb bbbb

dddd dddd

Read EEPROM Memory

1010 0000

xxxx xxxa

bbbb bbbb

oooo oooo

Write EEPROM Memory

1100 0000

xxxx xxxa

bbbb bbbb

dddd dddd

Read Lock and Fuse Bits

0101 1000

xxxx xxxx

xxxx xxxx

12Sx xxxF

Write Lock Bits

1010 1100

1111 1211

xxxx xxxx

xxxx xxxx

Read Signature Byte

0011 0000

xxxx xxxx

xxxx xxbb

oooo oooo

Write FSTRT Fuse

1010 1100

1011 111F

xxxx xxxx

xxxx xxxx

Legend:

a = address high bits; b = address low bits; H = 0 – low byte, 1 – high byte; o = data out; d = data in; x = don’t care bit; 1 = lock bit 1; 2 = lock bit 2; F = FSTRT fuse; S = SPIEN fuse

A.10 The Special Function Registers of 8051

ACC

A.7

A.6

A.5

A.4

A.3

A.2

A.1

A.0

B

B.7

B.6

B.5

B.4

B.3

B.2

B.1

B.0

PSW

CY

AC

F0

RS1

RS0

OV

–

P

SP

Stack Pointer

DPH

Data pointer – high byte

DPL

Data pointer – low byte

P0

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

P1

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

P3

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1

P3.0

IP

–

–

PT2

PS

PT1

PX1

PT0

PX0

IE

EA

–

ET2

ES

ET1

EX1

ET0

EX0

TMOD

GATE

C/T

M1

M0

GATE

C/T

M1

M0

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TH0

Timer0 data – high byte

TL0

Timer0 data – low byte

TH1

Timer1 data – high byte

TL1

Timer1 data – low byte

SCON

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SBUF

Serial data buffer

PCON

SMOD

–

–

–

GF1

GF0

PD

IDL

A.11 8051 Instruction Set

Arithmetic Instructions

Mnemonic

Operation

Description

Flags

ADD

A,Rn

Add register to Accumulator

A ← A + Rn

C,OV,AC

ADD

A.direct

Add direct byte to Accumulator

A ← A + direct

C,OV,AC

ADD

A,@Ri

Add indirect RAM to Accumulator

A ← A + (Ri )

C,OV,AC

ADD

A,#data

Add immediate data to Accumulator

A ← A + data

C,OV,AC

ADDC

A,Rn

Add register to Accumulator with Carry

A ← A + Rn + C

C,OV,AC

ADDC

A.direct

Add direct byte to Accumulator with Carry

A ← A + direct + C

C,OV,AC

ADDC

A,@Ri

Add indirect RAM to Accumulator with Carry

A ← A + (Ri ) + C

C,OV,AC

ADDC

A,#data

Add immediate data to Acc with Carry

2 A ← A + data + C

C,OV,AC

SUBB

A,Rn

Subtract Register from Acc with borrow

A ← A − Rn − C

C,OV,AC

SUBB

A.direct

Subtract direct byte from Acc with borrow

A ← A − direct − C

C,OV,AC

SUBB

A,@Ri

Subtract indirect RAM from Acc with borrow

A ← A − (Ri ) − C

C,OV,AC

SUBB

A,#data

Substract immediate data from Acc with borrow

A ← A − data − C

C,OV,AC

INC

A

Increment Accumulator

A ← A + 1

INC

Rn

Increment register

Rn ← Rn + 1

INC

Direct

Increment direct byte

direct ← direct + 1

INC

@Ri

Increment direct RAM

(Ri ) ← (Ri ) + 1

DEC

A

Decrement Accumulator

A ← A − 1

DEC

Rn

Decrement Register

Rn ← Rn − 1

DEC

Direct

Decrement direct byte

direct ← direct − 1

DEC

@Ri

Decrement indirect RAM

(Ri ) ← (Ri ) − 1

INC

DPTR

Increment Data Pointer

DPTR ← DPTR + 1

MUL

AB

Multiply A by B

A0−7,B15−8 ← AxB

C,OV

DIV

AB

Divide A by B

A0−7,B15−8 ← A / B

C,OV

DA

A

Decimal Adjust Accumulator

*see datasheet

C

Logic Instructions

Mnemonic

Operation

Description

Flags

ANL

A,Rn

AND Register to Accumulator

A ← A Λ Rn

ANL

A.direct

AND direct byte to Accumulator

A ← A Λ direct

ANL

A,@Ri

AND indirect RAM to Accumulator

A ← A Λ (Ri )

ANL

A,#data

AND immediate data to Accumulator

A ← A Λ data

ANL

direct.A

AND Accumulator to direct byte

direct ← direct Λ A

ANL

direct,#data

AND immediate data to direct byte

direct ← direct Λ data

ORL

A,Rn

OR register to Accumulator

A ← AV Rn

ORL

A.direct

OR direct byte to Accumulator

A ← A V Rn

ORL

A,@Ri

OR indirect RAM to Accumulator

A ← A V (Ri )

ORL

A,#data

OR immediate data to Accumulator

A ← A V data

ORL

direct.A

OR Accumulator to direct byte

direct ← direct V A

ORL

direct,#data

OR immediate data to direct byte

direct ← direct V data

XRL

A,Rn

Exclusive-OR register to Accumulator

A ← A V Rn

XRL

A.direct

Exclusive-OR direct byte to Accumulator

A ← A V Rn

XRL

A,@Ri

Exclusive-OR indirect RAM to Acc

A ← A V (Ri )

XRL

A,#data

Exclusive-OR immediate data to Accr

A ← A V data

XRL

direct.A

Exclusive-OR Accumulator to direct byte

direct ← direct V A

XRL

direct,#data

Exclusive-OR immediate data to direct byte

direct ← direct V data

CLR

A

Clear Accumulator

A ← 0

CPL

A

Complement Accumulator

A ← A V $FF

RL

A

Rotate Accumulator Left

A0 ← A7An+1 ← An A1 ← A0

RLC

A

Rotate Acc. Left through the Carry

A0 ← C,An+1 ← An ,C ← A7

C

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