ВУЗ: Не указан
Категория: Не указан
Дисциплина: Не указана
Добавлен: 14.06.2025
Просмотров: 3126
Скачиваний: 0
234 Appendices
Mnemonic |
Operation |
Description |
Flags |
RR |
A |
Rotate Accumulator Right |
RRC |
A |
Rotate Acc. Right through the Carry |
SWAP |
A |
Swap nibbles within the Accumulator |
A7 ← A0An ← An+1A6 ← A7
A7 ← C,An ← An+1,C ← A0 C A3−0 ↔ A7−4
Data Transfer Instructions
Mnemonic |
Operation |
Description |
Flags |
MOV |
A,Rn |
Move register to ccumulator |
MOV |
A.direct |
Move direct byte to accumulator |
MOV |
A,@Ri |
Move indirect RAM to Accumulator |
MOV |
A,#data |
Move immediate data to Accumulator |
MOV |
Rn ,A |
Move Accumulator to register |
MOV |
Rn ,direct |
Move direct byte to register |
MOV |
Rn ,#data |
Move immediate data to register |
MOV |
direct,A |
Move Accumulator to direct byte |
MOV |
direct, Rn |
Move register to direct byte |
MOV |
direct.direct |
Move direct byte to direct |
MOV |
direct,@Ri |
Move indirect RAM to direct byte |
MOV |
direct,#data |
Move immediate data to direct byte |
MOV |
@Ri ,A |
Move Accumulator to indirect RAM |
MOV |
@Ri ,direct |
Move direct byte to indirect RAM |
MOV |
@Ri ,#data |
Move immediate data to indirect RAM |
MOV |
DPTR,#data16 |
Load Data Pointer with a 16-bit constant |
MOVC |
A,@A + DPTR |
Move Code byte relative to DPTR to Acc |
MOVC |
A,@A + PC |
Move Code byte relative to PC to Acc |
MOVX |
A,@Ri |
Move External RAM (8-bit addr) to Acc |
MOVX |
A,@DPTR |
Move Exernal RAM (16-bit addr) to Acc |
MOVX |
@Ri ,A |
Move Acc to External RAM (8-bit addr) |
MOVX |
@DPTR,A |
Move Acc to External RAM (16-bit addr) |
PUSH |
Direct |
Push direct byte onto stack |
POP |
Direct |
Pop direct byte from stack |
XCH |
A,Rn |
Exchange register with Accumulator |
XCH |
A.direct |
Exchange direct byte with Acc |
XCH |
A,@R, |
Exchange indirect RAM with Acc |
XCHD |
A,@R, |
Exchange low-order Digit indirect RAM with Acc |
A ← Rn
A ← direct A ← (Ri ) A ← data Rn ← A
Rn ← direct Rn ← data direct ← A direct ← Rn direct ← direct direct ← (Ri ) direct ← data (Ri ) ← A
(Ri ) ← direct (Ri ) ← data DPTR ← data16
A ← (A + DPTR) A ← (A + PC)
A ← (Ri )
A ← (DPTR) (Ri ) ← A (DPTR) ← A STACK ← direct direct ← STACK A ↔ Rn
A ↔ direct A↔(Ri)
A3−0↔(Ri3−0)
Bit Manipulation Instructions
Mnemonic |
Operation |
Description |
Flags |
|
CLR |
C |
Clear Carry |
C ← 0 |
C |
CLR |
Bit |
Clear direct bit |
bit ← 0 |
|
SETB |
C |
Set Carry |
C ← 1 |
C |
SETB |
Bit |
Set direct bit |
bit ← 1 |
|
CPL |
C |
Complement Carry |
C ← 1 − C |
C |
CPL |
Bit |
Complement direct bit |
bit ← 1 − bit |
|
ANL |
C,bit |
AND direct bit to CARRY |
C ← C Λ bit |
C |
ANL |
C,/bit |
AND complement of direct bit to Carry |
C ← C Λ /bit |
C |
ORL |
C.bit |
OR direct bit to Carry |
C ← C V bit |
C |
ORL |
C,/bit |
OR complement of direct bit to Carry |
C ← C V /bit |
C |
MOV |
C.bit |
Move direct bit to Carry |
C ← bit |
C |
MOV |
bit.C |
Move Carry to direct bit |
bit ← C |
C |
A.11 |
8051 Instruction Set |
235 |
|||
Branch Instructions |
|||||
Mnemonic |
Operation |
Description |
Flags |
||
JC |
rel |
Jump if Carry is set |
If C = 1 |
||
PC = PC + rel |
|||||
JNC |
rel |
Jump if Carry not set |
If C = 0 |
||
PC = PC + rel |
|||||
JB |
bit.rel |
Jump if direct Bit is set |
If bit = 1 |
||
PC = PC + rel |
|||||
JNB |
bit.rel |
Jump if direct Bit is Not set |
If bit = 0 PC = PC + rel |
||
JBC |
bit.rel |
Jump if direct Bit is set and clear bit |
If bit = 1 |
||
PC = PC + rel,bit ← 0 |
|||||
ACALL |
addr 11 |
Absolute Subroutine Call |
PC = PC + 2 |
||
SP = SP + 1 |
|||||
(SP) ← PC7−0 |
|||||
SP = SP + 1 |
|||||
(SP) ← PC15−8 |
|||||
PC10−0 ← ADDR11 |
|||||
LCALL |
addr 16 |
Long Subroutine Call |
PC = PC + 2 |
||
SP = SP + 1 |
|||||
(SP) ← PC7−0 |
|||||
SP = SP + 1 |
|||||
(SP) ← PC15−8 |
|||||
PC15−0 ← ADDR16 |
|||||
RET |
Return from Subroutine |
PC15−8 ← (SP) |
|||
SP = SP − 1 |
|||||
PC7−0 ← (SP) |
|||||
SP = SP + 1 |
|||||
RETI |
Return from interrupt |
PC15−8 ← (SP) |
|||
SP = SP − 1 |
|||||
PC7−0 ← (SP) |
|||||
SP = SP + 1 |
|||||
EA ← 1 |
|||||
AJMP |
addr11 |
Absolute Jump |
PC = PC + 2 |
||
PC10−0 ← addr11 |
|||||
LJMP |
addr16 |
Long Jump |
PC15−0 ← addr16 |
||
SJMP |
rel |
Short Jump (relative addr) |
PC = PC + 2 |
||
@A + DPTR |
PC ← PC + rel |
||||
JMP |
Jump indirect relative to the DPTR |
PC ← A + DPTR |
|||
JZ |
rel |
Jump if Accumulator is Zero |
if A = 0 |
||
PC = PC + 2 |
|||||
PC ← PC + rel |
|||||
JNZ |
rel |
Jump if Accumulator is Not Zero |
if A = 0 |
||
PC = PC + 2 |
|||||
PC ← PC + rel |
|||||
CJNE |
A,direct,rel |
Compare direct byte to Acc and Jump |
if A = direct |
||
if Not Equal |
PC = PC + 2 |
||||
PC ← PC + rel |
C |
||||
CJNE |
A,#data,rel |
Compare immediate to Acc and Jump |
if A = data |
||
if Not Equal |
PC = PC + 2 |
||||
PC ← PC + rel |
C |
||||
CJNE |
Rn ,#data,rel |
Compare immediate to register and Jump |
if Rn = data |
||
if Not Equal |
PC = PC + 2 |
||||
PC ← PC + rel |
C |
||||
CJNE |
@Ri ,#data,rel |
Compare immediate to indirect and Jump |
if (RI ) = data |
||
if Not Equal |
PC = PC + 2 |
||||
PC ← PC + rel |
C |
||||
236 |
Appendices |
|||
Mnemonic |
Operation |
Description |
Flags |
|
DJNZ |
Rn ,rel |
Decrement register and Jump if Not Zero |
PC = PC + 2 |
|
Rn ← Rn − 1 |
||||
if Rn = 0 |
||||
PC = PC + rel |
||||
DJNZ |
direct,rel |
Decrement direct byte and Jump if Not Zero |
PC = PC + 2 |
|
direct ← direct −1 |
||||
if direct = 0 PC = PC + rel
Index n may take values in the range [0,7]. Index i may take values in the range [0,1].
A.12 An Example of 8051 Operating with External Bus
Figure A12.1 shows an example of a typical structure of 8051 operating with an external bus.
IC1 |
39 |
D0 |
D0 |
2 |
IC4 |
19 A0 |
A010 |
IC2 |
11 |
D0 |
IC3 |
||||||||||||||||
P0.0/AD0 |
1D |
1Q |
A0 |
O0 |
|||||||||||||||||||||||
P0.1/AD1 |
38 |
D1 |
D1 |
3 |
2D |
2Q |
18 A1 |
A1 9 |
A1 |
O1 |
12 |
D1 |
A0 |
10 |
A0 |
I/O0 |
11 |
D0 |
|||||||||
37 |
A2 8 |
13 |
12 |
||||||||||||||||||||||||
P0.2/AD2 |
D2 |
D2 |
4 |
3D |
3Q |
17 A2 |
A2 |
O2 |
D2 |
A1 |
9 |
A1 |
I/O1 |
D1 |
|||||||||||||
36 |
A3 7 |
15 |
A2 |
8 |
13 |
||||||||||||||||||||||
P0.3/AD3 |
D3 |
D3 |
5 |
4D |
4Q |
16 A3 |
A3 |
O3 |
D3 |
A2 |
I/O2 |
D2 |
|||||||||||||||
P0.4/AD4 |
35 |
D4 |
D4 |
6 |
5D |
5Q |
15 A4 |
A4 6 |
A4 |
O4 |
16 |
D4 |
A3 |
7 |
A3 |
I/O3 |
15 |
D3 |
|||||||||
34 |
A5 5 |
17 |
A4 |
6 |
16 |
||||||||||||||||||||||
P0.5/AD5 |
D5 |
D5 |
7 |
6D |
6Q |
14 A5 |
A5 |
O5 |
D5 |
A4 |
I/O4 |
D4 |
|||||||||||||||
P0.6/AD6 |
33 |
D6 |
D6 |
8 |
7D |
7Q |
13 A6 |
A6 4 |
A6 |
O6 |
18 |
D6 |
A5 |
5 |
A5 |
I/O5 |
17 |
D5 |
|||||||||
P0.7/AD7 |
32 |
D7 |
D7 |
9 |
8D |
8Q |
12 A7 |
A7 3 |
A7 |
O7 |
19 |
D7 |
A6 |
4 |
A6 |
I/O6 |
18 |
D6 |
|||||||||
A7 |
3 |
19 |
|||||||||||||||||||||||||
ALE 11 |
A8 |
25 |
A8 |
A7 |
I/O7 |
D7 |
|||||||||||||||||||||
21 |
24 |
||||||||||||||||||||||||||
P2.0/AD8 |
A8 |
C |
A9 |
A9 |
A8 |
25 |
A8 |
||||||||||||||||||||
22 |
21 |
24 |
|||||||||||||||||||||||||
P2.1/AD9 |
A9 |
1 |
OC |
A10 |
A10 |
A9 |
A9 |
||||||||||||||||||||
P2.2/AD10 |
23 |
A10 |
A11 |
23 |
A11 |
A10 |
21 |
A10 |
|||||||||||||||||||
P2.3/AD11 |
24 |
A11 |
74573 |
A12 2 |
A12 |
A11 |
23 |
A11 |
|||||||||||||||||||
25 |
|||||||||||||||||||||||||||
P2.4/AD12 |
A12 |
GND |
A13 |
26 |
A13 |
A12 |
2 |
A12 |
|||||||||||||||||||
P2.5/AD13 |
26 |
A13 |
A14 |
27 |
A14 |
A13 |
26 |
A13 |
|||||||||||||||||||
P2.6/AD14 |
27 |
A14 |
A15 1 |
A15 |
A14 |
1 |
A14 |
||||||||||||||||||||
P2.7/AD15 |
28 |
A15 |
20 |
CE\ |
WR\ |
27 |
|||||||||||||||||||||
WE\ |
|||||||||||||||||||||||||||
EA\ |
31 |
||||||||||||||||||||||||||
22 |
OE\ |
RD\ |
22 |
OE\ |
|||||||||||||||||||||||
ALE |
30 |
PSEN\ |
GND |
A15 |
20 |
CS\ |
|||||||||||||||||||||
PSEN\ |
29 |
27512 |
|||||||||||||||||||||||||
16 |
P3.6/WR\ |
62256 |
|||||||||||||||||||||||||
17 |
P3.7/RD\ |
GND |
|||||||||||||||||||||||||
AT89C51 |
|||||||||||||||||||||||||||
Fig. A12.1. 8051 operating with external bus
The EA\ signal is grounded, which means that the MCU ignores the internal program memory, if any.
A.13 Programming the Internal Memory of 8051
The waveforms of the signals involved in the process of programming the internal memory of 8051 are shown in Fig. A13.1.
ADDRESS |
Programming cycle |
Read cycle |
DATA |
DATA IN |
DATA OUT |
ALE/PROG
VPP
H
EA/VPP
L
P2.6, P2.7, P3.6, P3.7 |
P2.6, P2.7, P3.6, P3.7 |
Fig. A13.1. Waveforms for the signals involved in programming 8051 memory
The information in this section concerns those versions of 8051 microcontrollers that have internal EPROM or flash memory. Both EPROM (87C51) and flash (89C51) versions are programmable following the same principles. Only the value of the programming voltage Vpp differs. Note that any attempt to program the internal memory using inappropriate Vpp may cause permanent damage to the chip. See the specific data sheets for the exact requirements for Vpp.
Table A13.1 presents the status of the control signals for each particular operation. Besides these signals, during any program/verify operations, RST must be HIGH and PSEN\ must be LOW.
Table A13.1. Status of the control signals for program/read memory operations
Mode |
MCU Pins |
|||||
ALE/PROG |
EA/VPP |
P2.6 |
P2.7 |
P3.6 |
P3.7 |
|
READ MEMORY |
H |
H |
L |
L |
H |
H |
WRITE MEMORY |
H-L-H |
VPP |
L |
H |
H |
H |
READ SIGNATURE |
H |
H |
L |
L |
L |
L |
ERASE MEMORY 1 |
H-L-H 2 |
VPP |
H |
L |
L |
L |
WRITE LOCK BIT1 |
H-L-H |
VPP |
H |
H |
H |
H |
WRITE LOCK BIT2 |
H-L-H |
VPP |
H |
H |
L |
L |
WRITE LOCK BIT3 |
H-L-H |
VPP |
H |
L |
H |
L |
Legend:
1 – Only applicable for flash versions (89xxx series).
2 – Chip erase operations require 10 ms PROG pulse. H-L-H indicates a neagative pulse of 100 s, except the ERASE MEMORY operation, where this pulse must be 10 ms wide.