Файл: Microcontrollers in Practice (Mitescu M., 2005).pdf

Solution

Bits 7 and 6 of PORTD of HC11 are not implemented, and always read 0. By writing $38 = 00111000b to DDRD, bits 5, 4, 3 of PORTD are configured as output lines. Only these three bits are affected by subsequent write operations to PORTD. Read operations from an output port return the last value written to the port.

For this reason, the content of A after the final read from PORTD in the above example is 00110xxxb. The least significant three bits are input lines, and their status is determined by the logic levels on the external pins of the MCU.

SX 2.2

Write a code fragment to configure the upper nibble of PORTC of AT90S8535 as output, and the lower nibble as input, with the internal pull-up resistors enabled, then read the values of PINC0-3 and write them to PORTC4-7.

Solution

SX 2.3

Write a code fragment that configures the line P2.0 of a 8051 as input, then reads the status of this line, and writes the value read to P2.7.

Solution

additional stop bit is transmitted. This always has the status of the idle line. Figure 3.4. shows how the data line is sampled at the receiver.

The falling edge of the data line, corresponding to the start bit, starts the reception process.

The data line is sampled after half of the bit time interval to check for a valid start bit, and then at intervals equal to Tb. The values of the data line at these moments are shifted into the receiver data shift register Rx.

Important notes. The first bit transmitted in an asynchronous serial communication is the least significant bit (LSB).

The idle line status is HIGH.

The start bit always has the opposite polarity of the idle line, i. e. it is always 0. The stop bit always has the polarity of the idle line, i. e. it is always 1.

3.3 Error Detection in Asynchronous Communication

One serious problem when handling asynchronous serial communication is the vulnerability to electromagnetic interference. Several means have been provided to detect communication errors, and the status register of an asynchronous serial interface normally contains special status bits to indicate these errors.

If, for instance, when sampling the data line at the moment T0 + Tb/2 (refer to Fig. 3.4), a value of 1 is obtained, that means the falling edge detected at the moment T0 was not a valid start bit, but a spike due to electromagnetic noise. This type of error is called noise error.

Similarly, if the data line status at the moment T1 = T0 + Tb/2 + 9 × T b is not HIGH, this means that the expected stop bit is invalid, indicating that the byte received is in error. This type of error is called framing error.

Obviously, these two control methods are insufficient to detect all possible errors. Another method to verify the integrity of data is parity control. For this purpose, a special bit, called the parity bit, is transmitted just before the stop bit. This is either the most significant bit of each byte, or an additional ninth bit attached to each byte.

The values of the parity bits are automatically set so that the total number of 1s contained in the byte, plus the parity bit, is always an ODD or EVEN number, at the user’s choice. Both the transmitter and receiver must calculate the parity according to the same rule (ODD or EVEN). Upon reception of each byte, the parity is calculated, and, if the parity does not match the rule, the error is reported.

Parity control still cannot detect all errors, but, at the hardware level, the methods described above are all that can be done for error detection. For better error detection, software techniques must be used. Basically, software detection of communication errors relies on the following principles:

30 3 Using the Asynchronous Serial Interface

•The communication is based on data packets, having a determined structure.

•Each data packet contains a special field reserved for a sophisticated checksum. The transmitter computes the checksum for each packet and inserts it into the reserved field of the packet.

•The receiver recalculates the checksum of the packet and compares it with the value calculated by the transmitter and sent along with the packet. If the two values don’t match the packet is rejected, and the transmitter is requested to repeat the transmission of the packet.

This method is called Cyclic Redundancy Check Control (CRC). The algorithms used to compute the checksums are so complex that the probability that a packet with errors still has a correct checksum is extremely low.

3.4 The General Structure

of the Asynchronous Serial Communication Interface

The general block diagram of an asynchronous serial interface is presented in Fig. 3.5. This circuit is called a Universal Asynchronous Receiver Transmitter (UART). There are numerous stand-alone integrated circuits with this function, but most microcontrollers include a simplified version of UART, with the generic name Serial Communication Interface (SCI). This chapter contains details on the implementation of the SCI of HC11, AVR and 8051 microcontrollers. Even though there are differences in what concerns the names of the registers associated with the interface, or the names and particular functions of the control and status bits, the general structure of the interface is basically the same in all microcontrollers.

Internal bus

Fig. 3.5. General block diagram of the asynchronous serial communication interface

3.5 The Serial Communication Interface of 68HC11F1

SCDR – SCI Data Register

The transmitter’s and receiver’s data registers have the same address and the same name: Serial Communication Data Register (SCDR). Physically, they are distinct registers, but the write operations to SCDR are directed to the transmitter’s data

register, while the read operations from SCDR return the content of the receiver’s data register.

BAUD – Baud Rate Generator Control Register

To select the communication speed, a special register, called BAUD, has been provided. This controls how the system clock E is divided in the baud rate generator block, before it is applied to the control logic that actually generates the clock for the serial shift registers. The system clock is first applied to a programmable counter, called a prescaler. The prescaler output is then applied to a second programmable counter. After the two division stages the frequency of the resulting clock is 16 times the actual baud rate.

The BAUD register has the following structure:

•TCLR – Clear Baud Rate Counters – and RCKB – SCI Baud Rate Clock Check, are only used in special test operating mode.

•SCP[1:0] – SCI Baud Rate Prescaller Selects. These two bits control the prescaler division rate, as defined in Table 3.1.

•SCR[2:0] – SCI Baud Rate Selects. These bits control the second stage programmable counter of the baud generator, as shown in Table 3.2

Table 3.1. HC11 prescaler control bits

Table 3.2. HC11 baud rate select bits