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32 3 Using the Asynchronous Serial Interface

Example Knowing that the oscillator frequency is 8 MHz, and that the output frequency of the baud generator must be 16 times the actual baud rate, determine the value to write in the BAUD register in order to obtain 9600 baud communication speed.

Solution The input clock for the prescaler is the system clock E.

fE = fOSC/4 = 2 MHz = 2 000 000 Hz

The output clock must have the frequency:

f1 = 9600 × 16 = 153 600 Hz

This gives the global division rate: 2 000 000/153 600 = 13.

Choose the prescaler to divide by 13 (SCP1:SCP0 = 1:1), and the secondary counter to divide by 1 (SCR2:SCR1:SCR0 = 0:0:0). The resulting value for the BAUD register is 00110000b = 30H.

Note that for a given oscillator frequency, not all the possible baud rates can be obtained by programming the BAUD register.

With an 8-MHz oscillator clock it is impossible to obtain the baud rate of 19 200 bps, because the resulting global division rate is 6.5 (obviously, the division constant must be as close as possible to an integer value). The solution in this situation is to choose a different oscillator frequency. If, for example, the oscillator frequency is 7.3728 MHz, the global division rate required for 19 200 baud is 6, which can be easily obtained by choosing the prescaler to divide by 3, and the secondary counter to divide by 2.

SCSR – SCI Status Register

•TDRE – Transmitter Data Register Empty

This bit is automatically set when the transmitter’s data register is available for a write operation.

0 = SCDR busy

1 = SCDR ready for a new operation

•TC – Transmit Complete flag

The meaning of this bit is very similar to TDRE. The difference is that TC refers to any activity of the transmitter, including sending of break sequences on the serial line.

0 = Transmitter busy

1 = Transmitter ready

•RDRF – Receive Data Register Full Flag

0 = SCDR empty

1 = SCDR full

This flag indicates that a character has been received in SCDR and it is ready to be handled by software. RDRF is cleared by reading SCSR followed by a read of SCDR.

•IDLE – Rx Idle Line Detected Flag

0 = RxD line is active

1 = RxD line is idle

IDLE describes the status of the RxD line. It is set to 1 when RxD stays high for at least one character time. IDLE is cleared by reading SCSR then reading SCDR. Once cleared, it is not set again until the line becomes active, and then idles again.

•OR – Overrun Error Flag

0 = No overrun

1 = Overrun detected

This is an error flag. An overrun error occurs when all the bits of a new character

are received, and the previous character has not been handled by the software (RDRF = 1).

•NF – Noise Error Flag

One of the situations when this error flag is set has been described in Sect. 3.3. In fact, the reception data line is sampled several times during each Tb interval. NF is set when the samples corresponding to the same interval Tb have different values.

0 = character received without noise

1 = noise detected for the last character received

•FE – Framing Error

FE is set when a logic zero is detected in the position of the stop bit.

0 = Stop bit detected in the right position

1 = Zero detected instead of a stop bit

All error bits are cleared by reading SCSR followed by a read from SCDR.

SCCR1 – Serial Communications Control Register 1

This is the first of the two control registers of the interface. Only four bits are implemented in this register as follows:

34 3 Using the Asynchronous Serial Interface

The bits R8, T8, and M control the number of bits of the character transmitted/received over the interface. If the MODE bit M = 0, 8-bit characters are transmitted along with the corresponding start and stop bits. If M = 1, 9 data bits are transmitted for each character. The least significant 8 bits are placed in SCDR, and the most significant bit is T8 in case of a transmission operation and R8 in case of reception.

The control bit WAKE is related to an operating mode of the interface, which is specific to HC11, and will not be discussed in this book.

SCCR2 – Serial Communications Control Register 2

This register contains the main control bits of the interface

The most important control bits in this register are TE (Transmitter Enable) and RE (Receiver Enable).

When TE = 1, the whole transmitter subsystem is enabled. Similarly RE = 1 enables the receiver subsystem. These bits are cleared at RESET, therefore they must be set by software in the SCI initialization sequence.

The most significant four bits of this register, TIE, TCIE, RIE, ILIE, are local interrupt masks for SCI-related interrupts.

•TIE – Transmitter interrupt enable

0 = TDRE interrupts disabled

1 = An interrupt request is generated when TDRE = 1.

•TCIE – Transmit Complete Interrupt Enable

0 = TC interrupts disabled

1 = SCI interrupt requested when TC status flag is set

•RIE – Receiver Interrupt Enable

0 = RDRF and OR interrupts disabled

1 = SCI interrupt requested when RDRF (receiver data register full) flag or the OR (overrun error) bit in SCSR is set

•ILIE – Idle-Line Interrupt Enable

0 = IDLE interrupts disabled

1 = SCI interrupt requested when IDLE status flag is set

This bit is used in connection with the wake-up operating mode.

•RWU – Receiver Wakeup Control

0 = Normal SCI receiver

1 = Wakeup enabled and receiver interrupts inhibited

•SBK – Send Break 0 = Break generator off 1 = Break codes generated

Writing 1 to this bit of SCCR2 causes a break character to be generated, i. e. the TxD line is pulled to zero for at least one character time.

3.6 The Asynchronous Serial Communication Interface

of AVR Microcontrollers

The information in this paragraph refers to the microcontroller Atmel AT90S8535. Other members of the AVR family may have different structures of the asynchronous serial interfaces. See the data sheet for each specific microcontroller, for other models.

The data registers of the transmitter and receiver share the same address, just like in case of the HC11 microcontrollers. The two physical registers are accessible for the software as a single register, called UDR (UART Data Register). UDR is entirely similar to SCDR of HC11.

The equivalent of the BAUD register of HC11 is called UBRR (UART Baud Rate Register), for the AVR. The difference is that it is easier to use and much more flexible than the HC11 register. The clock frequency of the output signal of the baud rate generator is 16 times the actual baud rate, and is determined using the following formula:

where UBRR is the contents of UBRR, as written by software.

The status register of the interface is called the USR (UART Status Register) and has the following structure:

Here is the description of the status bits in USR:

•RXC – Reception Complete. This bit has a similar function to RDRF of the HC11. It is automatically set by hardware when a character is available in UDR. It is cleared by reading UDR, or when the associated interrupt is executed.

•TXC – Transmission Complete. This bit is set by hardware when the transmission of a character completes. It has a similar function to the TC flag of HC11. TXC is automatically cleared when the associated interrupt is executed or by writing 1 to the corresponding position of USR. This is the only Read/Write bit of USR. All other bits are Read Only.

•UDRE – USART Data Register Empty. This is the equivalent of the TDRE status bit of HC11, and indicates that the transmitter is ready to accept a new character.

36 3 Using the Asynchronous Serial Interface

•OR – Overrun, and FE – Framing Error, have exactly the same meaning as in HC11 SCSR. Unlike HC11, these bits are cleared only when a new character has been received and read correctly.

The control register of the interface UCR (UART Control Register) has the following structure:

•RXCIE, TXCIE, and UDRIE are local interrupt masks associated with the flags RXC, TXC, and UDRE, respectively. When a mask is set to 1 by software, the associated flag generates an interrupt when set to 1.

•TXE and RXE have identical functions with TE and RE of HC11. When TXE = 1 the transmitter is enabled, and RXE = 1 enables the receiver.

•CHR9 – this bit is similar to M from HC11. CHR9 = 1 indicates 9-bit transmission. In this case, RX8 and TX8 are the most significant bits of the transmitted/received characters.

3.7 The Asynchronous Serial Interface of 8051

The 8051 serial communication interface is less typical than those presented in the previous paragraphs. The first significant difference is that the baud rate generator is missing. It is replaced by one of the system timers.

The interface data register is called SBUF, and it is similar to the data register of HC11 and AVR. The control register of the interface, SCON, also contains several status bits. It has the following structure:

The bits SM[0:1] (Serial communication Mode control) select one of the four possible operating modes for the serial interface, as shown in Table 3.3.

Table 3.3. 8051 serial communication mode select bits